Patents by Inventor Mitsuko Takada

Mitsuko Takada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock jitter calculation device, clock jitter calculation method, and clock jitter calculation program
    Patent number: 7295938
    Abstract: In a voltage drop analysis step S101, the process calculates a temporal variation of a power source voltage supplied to each cell along a transmission path of a clock signal. In a delay variation rate ratio calculation step S102, the process calculates a delay time variation of each cell according to the power source voltage variation. In a clock delay variation amount calculation step S103, the process obtains the magnitude of jitter of the clock signal based on the delay time variation.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: November 13, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takafumi Nakashiba, Takahiro Ochi, Mitsuko Takada
  • Clock jitter calculation device, clock jitter calculation method, and clock jitter calculation program
    Publication number: 20060220751
    Abstract: In a voltage drop analysis step S101, the process calculates a temporal variation of a power source voltage supplied to each cell along a transmission path of a clock signal. In a delay variation rate ratio calculation step S102, the process calculates a delay time variation of each cell according to the power source voltage variation. In a clock delay variation amount calculation step S103, the process obtains the magnitude of jitter of the clock signal based on the delay time variation.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 5, 2006
    Inventors: Takafumi Nakashiba, Takahiro Ochi, Mitsuko Takada