Abstract: A processor unit equipped with an interface for externally outputting next instruction pointer data and next instruction code data from the processor unit is provided. With this processor unit, when a debugging unit is incorporated into a system LSI, the debugging unit can judge the break condition using the next instruction pointer data and the next instruction code data supplied from the processor unit for external use, so that duplicated hardware can be omitted.

Abstract: A data processing system of this invention includes at least one special purpose data processing unit having a data path portion for executing specific data process by a special purpose instruction and a general purpose data processing unit for executing processes by general purpose instructions. The data path portion of the special purpose data processing unit includes a plurality of registers, a processing part for performing an operation related to data stored in the registers and a register control part for selecting and performing input and/or output of data with respect to the registers from the general purpose data processing unit. Thus, function unit in a program, such as loop sentence can be compressed into one instruction and any conditions referred in the function unit can be flexibly set and changed.

Abstract: A data processing system is provided that includes a special purpose data processing unit (VU) specialized in a specific data processing according to a special purpose instruction, and a general purpose data processing unit (PU) capable of designating processes by general purpose instructions, and an instruction issue unit for supplying signals corresponding to the special purpose instruction and the general purpose instructions to the PU and the VU respectively, the instruction issue unit being an application-specific unit. By replacing the instruction issue unit with a sequencer specialized in the application, a reliable, compact, low-power consumption data processing system is provided in a short period using the resources resulting from optimization with the programmable VUPU processor capable of flexibly dealing with the specification change while maintaining the real-time response.