Patents by Inventor Mitsunobu Okano

Mitsunobu Okano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130245975
    Abstract: A drawing device includes a memory and a processor coupled to the memory. The processor executes a process including measuring voltages of planes of layers in a laminated circuit board and drawing the voltages of the planes that are measured on a graph having a voltage set on one axis and having a layer set on the other axis.
    Type: Application
    Filed: December 19, 2012
    Publication date: September 19, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Takashi KOBAYASHI, Mitsunobu OKANO, Shogo FUJIMORI, Hiroyuki ORIHARA
  • Patent number: 8065654
    Abstract: A computer aided design system is provided that includes a display, an input unit for inputting a circuit search-range narrowing condition, and a processing unit for, when a circuit topology of a circuit to be designed is changed, finding recommended circuits by searching a database, which stores part data and circuit data, based on the circuit search-range narrowing condition, and displaying a list of the recommended circuits on the display.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: November 22, 2011
    Assignee: Fujitsu Limited
    Inventors: Hidenobu Shiihara, Yasuhiro Yamashita, Mitsunobu Okano, Takashi Fukuda
  • Publication number: 20090125507
    Abstract: A computer aided design system is provided that includes a display, an input unit for inputting a circuit search-range narrowing condition, and a processing unit for, when a circuit topology of a circuit to be designed is changed, finding recommended circuits by searching a database, which stores part data and circuit data, based on the circuit search-range narrowing condition, and displaying a list of the recommended circuits on the display.
    Type: Application
    Filed: October 30, 2008
    Publication date: May 14, 2009
    Applicant: Fujitsu Limited
    Inventors: Hidenobu SHIIHARA, Yasuhiro Yamashita, Mitsunobu Okano, Takashi Fukuda
  • Patent number: 5790414
    Abstract: An automatic routing method and an automatic routing apparatus enable an optimum automatic routing under severe design conditions due to high-density mounting of an object of a wiring design such as an LSI, a multichip module, a printed wiring board, etc. The automatic routing apparatus has an area input unit for inputting area information for setting a routing controlled area in which an automatic routing is performed under specific routing control conditions within a wiring area of an object of the wiring design, a condition input unit for inputting condition information for designating the routing control conditions in the routing controlled area set according to the area information inputted from the area input unit, and an automatic routing unit for automatically routing under the specific routing control conditions designated according to the condition information inputted from the condition input unit within the routing controlled area.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: August 4, 1998
    Assignee: Fujitsu Limited
    Inventors: Mitsunobu Okano, Hiroshi Miura, Toshiyasu Sakata, Hiroyuki Orihara
  • Patent number: 5751597
    Abstract: A CAD apparatus for designing wires for an LSI or a printed circuit board is improved in that it can detect and determine a wire which is very probably influenced by crosstalk noise accurately in a short time and allows to make it clear how to modify wires. The CAD apparatus comprises a CAD execution section for designing wires, a display section for displaying a wire condition designed by the CAD execution section, and a display control section for controlling the displaying condition of the display section. The display control section controls the display section to display wire patterns of wires on the LSI or the printed circuit board obtained by designing of wires by the CAD execution section as well as the signal propagation directions of the individual wires.
    Type: Grant
    Filed: August 19, 1996
    Date of Patent: May 12, 1998
    Assignee: Fujitsu Limited
    Inventors: Mitsunobu Okano, Yasuhiro Yamashita
  • Patent number: 5644500
    Abstract: This invention is directed to a method and apparatus to find out an optimum solution in automatic routing or automatic placement with certainty and at a high-speed to improve a routing rate, and to realize automatic routing in a high-density. To these end, a routing approach is selected in a conversational mode while routing efficiency is consulted to compose routing processing procedure so as to generate a routing program. Besides, component placement processing procedures designated according to placement control information are combined to generate the placement program. A straight line between component pins adjacent to each other is defined as a chord, a wave for maze method routing is generated from a start point toward an end point of a routing path and propagated between the chords adjacent to each other.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: July 1, 1997
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Miura, Masato Ariyama, Kazuyuki Iida, Kazufumi Iwahara, Mitsunobu Okano, Hiroyuki Orihara, Akira Katsumata, Toshiyasu Sakata, Masaharu Nishimura, Hirofumi Hamamura, Naoki Murakami, Mitsuru Yasuda, Yasuhiro Yamashita, Ryouji Yamada, Atsushi Yamane