Patents by Inventor Mitsunori Abe
Mitsunori Abe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11435385Abstract: A specific conductivity measurement method includes: performing first measurement to obtain a resonance frequency f1 that is outputted to a measuring device when the first and second dielectric flat plates each have a thickness t1, and an unloaded Qu1 that corresponds to the resonance frequency f1; performing second measurement to obtain a resonance frequency f2 that is outputted to the measuring device when the first and second dielectric flat plates each have a thickness t2 that is different from the thickness t1, and an unloaded Qu2 that corresponds to the resonance frequency f2; and calculating a specific conductivity ?r of the copper foil and the first and second conductor flat plates based on an arithmetic equation that includes the resonance frequency the unloaded Qu1, the resonance frequency f2, and the unloaded Qu2.Type: GrantFiled: April 16, 2020Date of Patent: September 6, 2022Assignee: FUJITSU LIMITEDInventors: Kazuki Takahashi, Akiko Matsui, Kohei Choraku, Mitsunori Abe, Tetsuro Yamada, Yoshio Kobayashi, Sotaro Kobayashi
-
Publication number: 20210245093Abstract: A detoxification device has an inlet nozzle capable of reducing an amount of a deposit of an adhering metallic product and elongating a maintenance cycle and a detoxification device including the inlet nozzle. The inlet nozzle includes a portion adjacent to a combustor, that is cut (removed) in advance. Consequently, in the portion, an insulator made of a ceramic material is exposed. Since the ceramic material supplies a small number of electrons, even when the insulator is exposed to heat from the combustor to reach a high temperature, a reductive reaction is less likely to occur. Accordingly, even when a metallic exhaust gas is allowed to flow, the metallic exhaust gas is prevented from being precipitated as the metallic product and gradually deposited with time.Type: ApplicationFiled: June 3, 2019Publication date: August 12, 2021Inventors: Nobuo Mori, Mitsunori Abe, Masahiro Tanaka
-
Patent number: 11066206Abstract: Provided is a method for producing a self-adhesive to be arranged on a package comprising a space to store contents and an opening by which the space and an outside communicate, wherein the opening is repeatedly openable and sealable by the self-adhesive that consists of a cross-linking material of a resin composition containing a (meth)acrylic acid ester copolymer resin having a glass transition temperature of ?22.8° C. or more, and a crosslinking agent. The method comprises making the resin composition that contains the (meth)acrylic acid ester copolymer resin, and the crosslinking agent, the resin composition being either emulsion or dispersion; and cross-linking the resin composition.Type: GrantFiled: June 12, 2019Date of Patent: July 20, 2021Assignee: ZEON CORPORATIONInventors: Mitsunori Abe, Atsushi Sone
-
Patent number: 10929585Abstract: A recording medium recording a program for a process, the process includes: calculating an amount of distortion in a via of a printed circuit board based on an expression using coefficient m, ??={(L×?×?t×E)/(D×T)}×m, where ?? is the amount of distortion, L is a length of the via, ? is a thermal expansion coefficient of a base material, ?t is a temperature change of an environment, E is a Young's modulus, D is a diameter of the via, and T is a thickness of plating in the via; and calculating a lifetime of the via based on an expression, M=N/(n×365), where M is the lifetime of the via, n is a frequency of the temperature change, and N is the number of cycles of the lifetime satisfying an expression Nx=C/??.Type: GrantFiled: January 4, 2019Date of Patent: February 23, 2021Assignee: FUJITSU LIMITEDInventors: Mitsunori Abe, Yoshiyuki Hiroshima, Takahiro Kitagawa, Naoki Nakamura, Akiko Matsui
-
Patent number: 10882988Abstract: Provided is a vinyl chloride resin composition that enables production of a vinyl chloride resin molded product that can have a balance of excellent surface lubricity and excellent blooming resistance under normal temperature (23° C.) conditions. The vinyl chloride resin composition contains a vinyl chloride resin (a), a plasticizer (b), and a compound (c) indicated by the following formula (1): R1(NR2COR3)n. In formula (1), n is an integer of not less than 2 and not more than 6, R1 and R3 are each a hydrocarbon group, R2 is a hydrocarbon group or hydrogen, and at least one of the n-number of R3 groups is an unsaturated hydrocarbon group including at least one carbon-carbon unsaturated bond.Type: GrantFiled: February 5, 2018Date of Patent: January 5, 2021Assignee: ZEON CORPORATIONInventors: Shota Nishimura, Mitsunori Abe
-
Patent number: 10863629Abstract: A method of manufacturing a through hole of a substrate includes forming, to the substrate, a cutting hole surrounding a removal-target-part such that a connection part of the substrate remains, the connection part that connects the removal-target-part that is removed from the substrate and a remaining part other than the removal-target-part that has been removed, along a cutting line of the through hole formed to the substrate; applying plating on an area including an inner peripheral wall face of the cutting hole of the substrate; applying a film covering an opening of the cutting hole on a surface of the substrate applied with the plating and performing exposure and development of the film to form an etching resist covering an area including the opening of the cutting hole; performing etching of the plating applied on the substrate; removing the etching resist; and cutting the connection part to remove the removal-target-part.Type: GrantFiled: July 17, 2019Date of Patent: December 8, 2020Assignee: FUJITSU LIMITEDInventors: Kiyoyuki Hatanaka, Shigeru Sugino, Takahiro Kitagawa, Ryo Kanai, Nobuo Taketomi, Mitsunori Abe
-
Publication number: 20200341042Abstract: A specific conductivity measurement method includes: performing first measurement to obtain a resonance frequency f1 that is outputted to a measuring device when the first and second dielectric flat plates each have a thickness t1, and an unloaded Qu1 that corresponds to the resonance frequency f1; performing second measurement to obtain a resonance frequency f2 that is outputted to the measuring device when the first and second dielectric flat plates each have a thickness t2 that is different from the thickness t1, and an unloaded Qu2 that corresponds to the resonance frequency f2; and calculating a specific conductivity ?r of the copper foil and the first and second conductor flat plates based on an arithmetic equation that includes the resonance frequency the unloaded Qu1, the resonance frequency f2, and the unloaded Qu2.Type: ApplicationFiled: April 16, 2020Publication date: October 29, 2020Applicant: FUJITSU LIMITEDInventors: Kazuki TAKAHASHI, AKIKO MATSUI, Kohei Choraku, Mitsunori Abe, Tetsuro Yamada, Yoshio Kobayashi, Sotaro Kobayashi
-
Patent number: 10783309Abstract: An information processing device includes a processor that calculates a distortion amount that represents an amount of distortion generated in a via of a printed circuit board based on a following equation, ??={(L×?×?t×E)/(D×T)}×m×?×?×?; calculates a lifetime of the via based on a following equation, M=N/(n×365); changes, when the calculated lifetime is outside a first setting range, at least two design values of the via length, the thermal expansion coefficient, the Young's modulus, the via diameter, or the plating thickness within a second setting range corresponding to the at least two design values respectively; gives points of two perspectives affected by the change and outputs a graph that indicates an impact degree according to the points of the two perspectives for each combination of the at least two design values.Type: GrantFiled: July 3, 2019Date of Patent: September 22, 2020Assignee: FUJITSU LIMITEDInventors: Mitsunori Abe, Yoshiyuki Hiroshima, Takahiro Kitagawa, Akiko Matsui, Naoki Nakamura
-
Patent number: 10624216Abstract: A wiring board includes, a base plate that has a first surface, a second surface opposite to the first surface, and a side surface coupled to the first surface and the second surface, a conductor provided on the side surface, and a protrusion provided over the side surface. The protrusion partitions the conductor into a first portion on the side surface that extends to the first surface and a second portion on the side surface that extends to the second surface. The protrusion has a solder wettability lower than the conductor and protrudes from the conductor.Type: GrantFiled: October 3, 2018Date of Patent: April 14, 2020Assignee: FUJITSU LIMITEDInventors: Nobuo Taketomi, Takahiro Kitagawa, Mitsunori Abe, Shigeru Sugino, Kiyoyuki Hatanaka, Shigeo Iriguchi, Ryo Kanai
-
Publication number: 20200037452Abstract: A method of manufacturing a through hole of a substrate includes forming, to the substrate, a cutting hole surrounding a removal-target-part such that a connection part of the substrate remains, the connection part that connects the removal-target-part that is removed from the substrate and a remaining part other than the removal-target-part that has been removed, along a cutting line of the through hole formed to the substrate; applying plating on an area including an inner peripheral wall face of the cutting hole of the substrate; applying a film covering an opening of the cutting hole on a surface of the substrate applied with the plating and performing exposure and development of the film to form an etching resist covering an area including the opening of the cutting hole; performing etching of the plating applied on the substrate; removing the etching resist; and cutting the connection part to remove the removal-target-part.Type: ApplicationFiled: July 17, 2019Publication date: January 30, 2020Applicant: FUJITSU LIMITEDInventors: Kiyoyuki Hatanaka, Shigeru Sugino, Takahiro Kitagawa, Ryo Kanai, Nobuo Taketomi, Mitsunori Abe
-
Publication number: 20200026816Abstract: An information processing device includes a processor that calculates a distortion amount that represents an amount of distortion generated in a via of a printed circuit board based on a following equation, ??={(L×?×?t×E)/(D×T)}×m×?×?×?; calculates a lifetime of the via based on a following equation, M=N/(n×365); changes, when the calculated lifetime is outside a first setting range, at least two design values of the via length, the thermal expansion coefficient, the Young's modulus, the via diameter, or the plating thickness within a second setting range corresponding to the at least two design values respectively; gives points of two perspectives affected by the change and outputs a graph that indicates an impact degree according to the points of the two perspectives for each combination of the at least two design values.Type: ApplicationFiled: July 3, 2019Publication date: January 23, 2020Applicant: FUJITSU LIMITEDInventors: Mitsunori Abe, YOSHIYUKI HIROSHIMA, Takahiro KITAGAWA, AKIKO MATSUI, Naoki Nakamura
-
Publication number: 20190390048Abstract: Provided is a vinyl chloride resin composition that enables production of a vinyl chloride resin molded product that can have a balance of excellent surface lubricity and excellent blooming resistance under normal temperature (23° C.) conditions. The vinyl chloride resin composition contains a vinyl chloride resin (a), a plasticizer (b), and a compound (c) indicated by the following formula (1): R1(NR2COR3)n. In formula (1), n is an integer of not less than 2 and not more than 6, R1 and R3 are each a hydrocarbon group, R2 is a hydrocarbon group or hydrogen, and at least one of the n-number of R3 groups is an unsaturated hydrocarbon group including at least one carbon-carbon unsaturated bond.Type: ApplicationFiled: February 5, 2018Publication date: December 26, 2019Applicant: ZEON CORPORATIONInventors: Shota NISHIMURA, Mitsunori ABE
-
Publication number: 20190291915Abstract: Provided is a method for producing a self-adhesive to be arranged on a package comprising a space to store contents and an opening by which the space and an outside communicate, wherein the opening is repeatedly openable and sealable by the self-adhesive that consists of a cross-linking material of a resin composition containing a (meth)acrylic acid ester copolymer resin having a glass transition temperature of ?22.8° C. or more, and a crosslinking agent. The method comprises making the resin composition that contains the (meth)acrylic acid ester copolymer resin, and the crosslinking agent, the resin composition being either emulsion or dispersion; and cross-linking the resin composition.Type: ApplicationFiled: June 12, 2019Publication date: September 26, 2019Applicant: ZEON CORPORATIONInventors: Mitsunori ABE, Atsushi SONE
-
Patent number: 10393797Abstract: A method for inspecting a laminated board, includes: performing a reflow process to solder an electronic component to a surface of a laminated board in which at least one of a plurality of wiring layers which are laminated with each other is coupled to another adjacent wiring layer via a via; and inspecting, in the reflow process, a conduction state of the via after a temperature of the laminated board reaches a melting point of a solder, and when the temperature of the laminated board is at a temperature range lower than the melting point and higher than room temperature.Type: GrantFiled: June 15, 2017Date of Patent: August 27, 2019Assignee: FUJITSU LIMITEDInventors: Mitsunori Abe, Takahiro Kitagawa, Shigeo Iriguchi, Kiyoyuki Hatanaka, Shigeru Sugino, Ryo Kanai
-
Publication number: 20190220564Abstract: A recording medium recording a program for a process, the process includes: calculating an amount of distortion in a via of a printed circuit board based on an expression using coefficient m, ??={(L×?×?t×E)/(D×T)}×m, where ?? is the amount of distortion, L is a length of the via, ? is a thermal expansion coefficient of a base material, ?t is a temperature change of an environment, E is a Young's modulus, D is a diameter of the via, and T is a thickness of plating in the via; and calculating a lifetime of the via based on an expression, M=N/(n×365), where M is the lifetime of the via, n is a frequency of the temperature change, and N is the number of cycles of the lifetime satisfying an expression Nx=C/??.Type: ApplicationFiled: January 4, 2019Publication date: July 18, 2019Applicant: FUJITSU LIMITEDInventors: Mitsunori ABE, YOSHIYUKI HIROSHIMA, Takahiro KITAGAWA, Naoki NAKAMURA, AKIKO MATSUI
-
Patent number: 10342129Abstract: A substrate includes an insulation layer including a glass cloth impregnated with a resin, and a through hole having a hole included in the insulation layer and plating formed in an inner surface of the hole, where a location, intersecting with the glass cloth, of an outer circumferential portion of the through hole has a recessed portion recessed toward an outside of the hole.Type: GrantFiled: April 5, 2018Date of Patent: July 2, 2019Assignee: FUJITSU LIMITEDInventors: Shigeo Iriguchi, Takahiro Kitagawa, Mitsunori Abe, Shigeru Sugino, Nobuo Taketomi, Kiyoyuki Hatanaka, Ryo Kanai
-
Publication number: 20190110365Abstract: A wiring board includes, a base plate that has a first surface, a second surface opposite to the first surface, and a side surface coupled to the first surface and the second surface, a conductor provided on the side surface, and a protrusion provided over the side surface. The protrusion partitions the conductor into a first portion on the side surface that extends to the first surface and a second portion on the side surface that extends to the second surface. The protrusion has a solder wettability lower than the conductor and protrudes from the conductor.Type: ApplicationFiled: October 3, 2018Publication date: April 11, 2019Applicant: FUJITSU LIMITEDInventors: Nobuo Taketomi, Takahiro KITAGAWA, Mitsunori Abe, Shigeru SUGINO, Kiyoyuki Hatanaka, Shigeo Iriguchi, Ryo Kanai
-
Publication number: 20180310405Abstract: A substrate includes an insulation layer including a glass cloth impregnated with a resin, and a through hole having a hole included in the insulation layer and plating formed in an inner surface of the hole, where a location, intersecting with the glass cloth, of an outer circumferential portion of the through hole has a recessed portion recessed toward an outside of the hole.Type: ApplicationFiled: April 5, 2018Publication date: October 25, 2018Applicant: FUJITSU LIMITEDInventors: Shigeo Iriguchi, Takahiro KITAGAWA, Mitsunori Abe, Shigeru SUGINO, Nobuo Taketomi, Kiyoyuki Hatanaka, Ryo Kanai
-
Publication number: 20180148214Abstract: Provided is a package comprising: a space to store contents; and an opening by which the space and an outside communicate, wherein the opening is repeatedly openable and sealable by a self-adhesive (E) that is made by cross-linking a resin composition (C) containing a (meth)acrylic acid ester copolymer resin (A), and a crosslinking agent (B), the package being repeatedly sealable after opened first time.Type: ApplicationFiled: April 28, 2016Publication date: May 31, 2018Applicant: ZEON CORPORATIONInventors: Mitsunori ABE, Atsushi SONE
-
Publication number: 20180059170Abstract: A method for inspecting a laminated board, includes: performing a reflow process to solder an electronic component to a surface of a laminated board in which at least one of a plurality of wiring layers which are laminated with each other is coupled to another adjacent wiring layer via a via; and inspecting, in the reflow process, a conduction state of the via after a temperature of the laminated board reaches a melting point of a solder, and when the temperature of the laminated board is at a temperature range lower than the melting point and higher than room temperature.Type: ApplicationFiled: June 15, 2017Publication date: March 1, 2018Applicant: FUJITSU LIMITEDInventors: Mitsunori ABE, Takahiro Kitagawa, Shigeo Iriguchi, Kiyoyuki Hatanaka, Shigeru Sugino, Ryo Kanai