Abstract: A method of manufacturing a semiconductor device including mounting semiconductor chips, each chip having pads, on respective areas of a front surface of an assembly substrate, electrically connecting corresponding terminals on a rear surface of the assembly substrate through wirings of the assembly substrate to the pads of the semiconductor chips, respective terminals and wirings electrically connected to a semiconductor chip being confined within the corresponding area of the assembly substrate on which the semiconductor chip is mounted, inputting test waveforms to the pads of the plurality of semiconductor chips through the corresponding terminals and wirings and testing the semiconductor chips, and, after the testing the semiconductor chips, cutting the assembly substrate with a rotating blade into pieces corresponding to the respective areas. The terminals and wirings connecting the terminals to the semiconductor chips are not cut by the rotating blade.

Abstract: An assembly substrate, on which semiconductor chips, each having a terminal receiving a burn-in test waveform, are arranged, is detachably attached to a burn-in test adapter. The burn-in test adapter has wiring for, when an assembly substrate is attached to the burn-in test adapter, making an electrical contact with the terminal of each of the semiconductor chips on the assembly substrate. Moreover, the burn-in test adapter has a burn-in test terminal that is electrically connected to the wiring and that receives the burn-in test waveform.

Abstract: A logical simulation device has a delay value calculations section to calculate delay values of circuit blocks in a semiconductor integrated circuit as a target of logical simulation based on logical circuit information relating to the logical circuit blocks, input test patterns as operational descriptions of used in circuit verification, and delay value calculation information stored in a delay value and timing check value calculation library, and a logical simulation section performs the logical simulation of the semiconductor integrated circuit based on the calculated delay values.

Abstract: At Step S1, the circuit forming the semiconductor integrated circuit to be designed is divided into sub circuits, and the area sizes and the positions of blocks to seat the sub circuits are determined on a chip. At Step S2, only flip-flops are counted as cells which are assumed to be the source of heat. At Step S3, a heat quantity per unit area in each block (i.e., average heat quantity) is calculated for each sub circuit. More specifically, average heat quantities are calculated from the area sizes of the blocks, the number of the flip-flops of each sub circuit, and the amount of heat generated in each flip-flop during operation of the flip-flop. Heat generated in a semiconductor integrated circuit is estimated easily by considering only a clock signal.