Abstract: The drive control device includes a display control part and a touch control part. The display control part includes a control circuit operable to control first and second frame modes, and a clock pulse generator operable to produce a display line clock signal in synchronization with a display line switching cycle. The control circuit changes display and non-display drive terms in start timing on an individual display frame period basis in the first frame mode. In the second frame mode, each display frame period includes only one display drive term; the display drive term is not interrupted by a non-display drive term halfway. The second frame mode is arranged so that the cycle of the display line clock signal in synchronization with the display line switching cycle is made longer than that in the first frame mode.

Abstract: The drive control device includes a display control part and a touch control part. The display control part includes a control circuit operable to control first and second frame modes, and a clock pulse generator operable to produce a display line clock signal in synchronization with a display line switching cycle. The control circuit changes display and non-display drive terms in start timing on an individual display frame period basis in the first frame mode. In the second frame mode, each display frame period includes only one display drive term; the display drive term is not interrupted by a non-display drive term halfway. The second frame mode is arranged so that the cycle of the display line clock signal in synchronization with the display line switching cycle is made longer than that in the first frame mode.

Abstract: A clock data recovery (CDR) circuit is provided with a circuit that updates a locked oscillation frequency, with a small loop gain, after phase lock based on a phase-locked loop circuit for a frequency-locked frequency is completed by a frequency-locked loop circuit or during a phase lock operation. Since the locked oscillation frequency is updated with a small loop gain, it is possible to correct a fluctuation in a frequency of an oscillation circuit in the frequency-locked loop circuit without oscillating a phase-locked loop undesirably even during a phase lock operation.

Abstract: A clock data recovery (CDR) circuit is provided with a circuit that updates a locked oscillation frequency, with a small loop gain, after phase lock based on a phase-locked loop circuit for a frequency-locked frequency is completed by a frequency-locked loop circuit or during a phase lock operation. Since the locked oscillation frequency is updated with a small loop gain, it is possible to correct a fluctuation in a frequency of an oscillation circuit in the frequency-locked loop circuit without oscillating a phase-locked loop undesirably even during a phase lock operation.

Abstract: The decoding apparatus includes an ACS unit to execute an add-compare-select operation on encoded received data, and an error detector to detect whether there is an error in decoded data calculated based on the executed add-compare-select operation, and if there is an error in the decoded data, the ACS unit additionally executes the add-compare-select operation on the received data.

Abstract: For the coded data that was transmitted via a communication channel, a known code portion thereof that is a code portion corresponding to known data is detected. When the known code portion is not detected from the coded data, the coded data will be decoded. When the known code portion is detected from the coded data, at least a part thereof will be replaced with normal data, and the decoding will be performed on the coded data after the substitution.

Abstract: The present invention provides a communication device and receiving method in which a scale of circuit and power consumption can be reduced. A parameter calculating section 62 calculates parameters with respect to specifying resource blocks (RB) to which a physical downlink shared channel (PDSCH) is mapped. A counter 63 and an interleaver 64 convert a virtual resource block (VRB) number to a physical resource block (PRB) number only by add-subtract calculation, shift operation, and comparison with reference to the calculated parameters. The present invention can be applied to a communication device complying with 3rd Generation Partnership Project (3GPP).

Abstract: The decoding apparatus includes an ACS unit to execute an add-compare-select operation on encoded received data, and an error detector to detect whether there is an error in decoded data calculated based on the executed add-compare-select operation, and if there is an error in the decoded data, the ACS unit additionally executes the add-compare-select operation on the received data.

Abstract: For the coded data that was transmitted via a communication channel, a known code portion thereof that is a code portion corresponding to known data is detected. When the known code portion is not detected from the coded data, the coded data will be decoded. When the known code portion is detected from the coded data, at least a part thereof will be replaced with normal data, and the decoding will be performed on the coded data after the substitution.

Abstract: A de-interleaver has a TTI frame buffer storing a TTI frame before de-interleaving, a P bit information table storing P bit information containing the size and added position of P bits to be added to the TTI frame before de-interleaving, and a permutation rule table storing permutation rules of de-interleaving. The de-interleaver performs de-interleaving on the data stored in the TTI frame buffer based on the P bit information stored in the P bit information table and the permutation rules stored in the permutation rule table.

Abstract: A decoding method relative to this application improves an error correction performance without increasing a memory. The decoding method includes obtaining a first decoded result from a first decoding path being on a trellis diagram; determining whether the first decoded result is incorrect or not; creating a second decoding path when the first decoded result is incorrect; and obtaining a second decoded result from the second decoding path.

Abstract: To provide transport format detecting apparatus and method capable of reducing a period necessary for detecting a transport format and saving current consumption. A transport format detecting apparatus according to an embodiment of the invention includes: a Viterbi decoding unit calculating likelihood information of a plurality of paths up to each state of a trellis diagram based on a received sequence to generate a decoded sequence; a differential operational unit calculating a difference between the likelihood information in each state; a decoding control unit stopping generation of decoded sequence with the Viterbi decoding unit based on the difference between the likelihood information; and a transport format output unit detecting a transport format based on a size of the generated decoded sequence.

Abstract: A de-interleaver has a TTI frame buffer storing a TTI frame before de-interleaving, a P bit information table storing P bit information containing the size and added position of P bits to be added to the TTI frame before de-interleaving, and a permutation rule table storing permutation rules of de-interleaving. The de-interleaver performs de-interleaving on the data stored in the TTI frame buffer based on the P bit information stored in the P bit information table and the permutation rules stored in the permutation rule table.