Abstract: By switching a mode signal, capability of a drive circuit in a latch circuit can be improved than in a normal mode. Accordingly, even if a small leakage occurs in a blown portion of a fuse element, blow is correctly identified. In this manner, by improving drivability of the latch circuit, incorrect determination of fuse blow state can be avoided. Thus, a semiconductor device unlikely to make incorrect determination of fuse blow state can be provided.

Abstract: By switching a mode signal, capability of a drive circuit in a latch circuit can be improved than in a normal mode. Accordingly, even if a small leakage occurs in a blown portion of a fuse element, blow is correctly identified. In this manner, by improving drivability of the latch circuit, incorrect determination of fuse blow state can be avoided. Thus, a semiconductor device unlikely to make incorrect determination of fuse blow state can be provided.

Abstract: A first repair chip, wherein BANK 2 functions properly although BANKs 0, 1 and 3 have become defective, and a second repair chip, wherein BANKs 1, 2 and 3 function properly although BANK 0 has become defective, are mounted on a rear surface of a module substrate in order to substitute for the functions of BANK 2 of the first bare chip and of BANKs 1 and 2 of the second bare chip that have become defective on the front surface of the module substrate. Thereby, a semiconductor memory module is obtained that can be repaired by mounting chips that carry out functions substituting for those of defective banks while effectively utilizing the functions of other banks that are not defective.

Abstract: A double phase comparator sets both first and second signals to an “L” level in order to delay a phase of a feedback clock signal when the feedback clock signal is at the “H” level and the “L” level at the rising and falling edges of an internal clock signal, respectively. The double phase comparator also sets both first and third signals to the “L” levels in order to advance a phase of a feedback clock signal when the feedback clock signal is at the “L” level and the “H” level at the rising and falling edges of an internal clock signal, respectively. Moreover, the double phase comparator sets the first signal to the “H” level in order to stop a phase control of the feedback clock signal when the feedback clock signal is at the same level at the rising and falling edges of an internal clock signal.

Abstract: In a semiconductor integrated circuit having a DRAM, a DWL driver circuit has a bias function unit (42, 43) for supplying, as a potential of a word line, a sub decode signal of an H level in an active state and an L level signal of a ground potential in a standby state, and switching the potential of the word line to a low potential for self refresh which is higher than the ground potential only by a very small value (+&agr;volts) in a self refresh mode. Thus, a refresh cycle is extended to thereby reduce a self refresh current.

Abstract: A plurality of internal circuits each include a respective clock adjusting circuit that adjusts the phase of a clock signal given by a clock buffer. Even if a difference in delayed amount of the clock signal is generated by drawing clock interconnections, a different adjustment can be made for each internal circuit, whereby the operation of synchronized circuits respectively included in the plurality of internal circuits can be improved.

Abstract: A first repair chip, wherein BANK 2 functions properly although BANKs 0, 1 and 3 have become defective, and a second repair chip, wherein BANKs 1, 2 and 3 function properly although BANK 0 has become defective, are mounted on a rear surface of a module substrate in order to substitute for the functions of BANK 2 of the first bare chip and of BANKs 1 and 2 of the second bare chip that have become defective on the front surface of the module substrate. Thereby, a semiconductor memory module is obtained that can be repaired by mounting chips that carry out functions substituting for those of defective banks while effectively utilizing the functions of other banks that are not defective.

Abstract: In a semiconductor integrated circuit having a DRAM, a DWL driver circuit has a bias function unit (42, 43) for supplying, as a potential of a word line, a sub decode signal of an H level in an active state and an L level signal of a ground potential in a standby state, and switching the potential of the word line to a low potential for self refresh which is higher than the ground potential only by a very small value (+&agr;volts) in a self refresh mode. Thus, a refresh cycle is extended to thereby reduce a self refresh current.

Abstract: A double phase comparator sets both first and second signals to the “L” levels to delay a phase of a feedback clock signal when the feedback clock signals at rising and falling edges of an internal clock signal are at the “H” level and the “L” level respectively, or sets both first and third signals to the “L” levels to advance a phase of a feedback clock signal when the feedback clock signals at both edges are at the “L” level and the “H” level respectively, or sets the first signal to the “H” level to stop a phase control of the feedback clock signal when the levels of the feedback clock signal at both edges correspond.

Abstract: A semiconductor memory device uses in a test mode a clock signal from a tester to allow a test clock conversion circuit and a DLL circuit to generate a rapid internal clock. The internal clock is applied to serial-parallel conversion circuits subjecting received, packetized data to serial-parallel conversion, and an interface circuit receiving and decoding outputs from the serial-parallel conversion circuits and outputting a command such as ACT to a DRAM core. Furthermore, an internal packet generation circuit uses the internal clock to rapidly generate a testing packet signal. Thus the device's operation can be checked with a low speed tester, without externally receiving a rapid packet signal.

Abstract: A main computer on a maker side carries out a grading selling of products managed by identification numbers in response to a request from a user terminal. A user is provided with grading information of the products. The main computer receives a purchase order from a user terminal with a requirement that the user is a registered member. The main computer also receives complaint information and inquiries from the user terminal. Data in a product management file is used to reconfigure tests before shipment.

Abstract: A semiconductor memory device uses in a test mode a clock signal from a tester to allow a test clock conversion circuit and a DLL circuit to generate a rapid internal clock. The internal clock is applied to serial-parallel conversion circuits subjecting received, packetized data to serial-parallel conversion, and an interface circuit receiving and decoding outputs from the serial-parallel conversion circuits and outputting a command such as ACT to a DRAM core. Furthermore, an internal packet generation circuit uses the internal clock to rapidly generate a testing packet signal. Thus the device's operation can be checked with a low speed tester, without externally receiving a rapid packet signal.

Abstract: A semiconductor integrated circuit includes: first and second counters activated upon receipt of a low level signal and outputting a signal with a period which is twice that of the signal input; first fuse circuits connected to first counters; and a second fuse circuit connected to second counter. First counters are inactivated when fuses included in first fuse circuits are disconnected, and second counter is activated when a fuse included in second fuse circuit is disconnected. Thus, the period of a signal for determining a refresh period can be efficiently adjusted. Here, the arrangement of first fuse circuits and a second fuse circuit can be converse.

Abstract: A plurality of internal circuits each include a respective clock adjusting circuit that adjusts the phase of a clock signal given by a clock buffer. Even if a difference in delayed amount of the clock signal is generated by drawing clock interconnections, a different adjustment can be made for each internal circuit, whereby the operation of synchronized circuits respectively included in the plurality of internal circuits can be improved.

Abstract: A semiconductor memory device uses in a test mode a clock signal from a tester to allow a test clock conversion circuit and a DLL circuit to generate a rapid internal clock. The internal clock is applied to serial parallel conversion circuits subjecting received, packetized data to serial parallel conversion, and an interface circuit receiving and decoding outputs from the serial-parallel conversion circuits and outputting a command such as ACT to a DRAM core. Furthermore, an internal packet generation circuit uses the internal clock to rapidly generate a testing packet signal. Thus the device's operation can be checked with a low speed tester, without externally receiving a rapid packet signal.

Abstract: In a circuit producing a reference voltage that is used in an internal circuit having an operation mode switched by utilizing a MOS transistor receiving a constant voltage on its gate, a signal changing in a direction controlling a voltage change caused on a gate node is applied to the gate or a drain of the MOS transistor receiving the constant voltage on the gate when the operation mode is switched. The constant voltage can be suppressed from varying through capacitive coupling of a parasitic capacitance of the constant voltage MOS transistor when the operation mode is switched, so that the reference voltage can be stably produced.

Abstract: A semiconductor device is obtained in which initial breakdown voltage of an insulating film is improved. On a silicon substrate, an insulating film is provided which is not more than 100 .ANG. in thickness. An electrode is provided on the silicon substrate, with the insulating film positioned therebetween. Oxygen concentration in the substrate is set to be not more than 1.times.10.sup.18 atoms/cm.sup.3 by old ASTM value.

Abstract: It is an object to obtain evaluation results with a dielectric film evaluating test structure which are close to those with an actual device. Gate electrodes (6A) are provided in a dielectric film evaluating test structure. In the gate electrodes 6A, openings (20) are formed on a gate insulator film (5) by etching, or the like.