Patents by Inventor Mitsunori Yokoyama

Mitsunori Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11934305
    Abstract: According to an embodiment, when receiving a read request designating a logical address range of a particular size or more from a host, a first circuit issues a plurality of first sub-commands, each of which is a sub-command for each first data unit, in order of logical addresses. A second circuit respectively adds serial numbers corresponding to the plurality of first sub-commands in the order of issuance. A plurality of third circuits respectively executes processing of specifying locations of the first data unit based on management information for the plurality of first sub-commands in a distributed manner. A fifth circuit reorders the plurality of first sub-commands in the logical address order based on the serial numbers after the processing by the plurality of third circuits. A sixth circuit executes a read operation on a first memory based on the plurality of first sub-commands reordered in the order of logical addresses.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: March 19, 2024
    Assignee: Kioxia Corporation
    Inventors: Toru Motoya, Mitsunori Tadokoro, Tomonori Yokoyama, Fuyuki Ichiba, Kensuke Minato, Kimihisa Oka
  • Patent number: 10712149
    Abstract: A DPTSS fiber optic cable includes an optical fiber sheathing cylindrical metal tube accommodating a pressure sensor optical fiber and having a plurality of through holes formed therein; and pressure blocking sections formed at intervals in the axial direction of the cable.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: July 14, 2020
    Assignee: NEUBREX CO., LTD.
    Inventors: Kinzo Kishida, Yoshiaki Yamauchi, Mitsunori Yokoyama
  • Publication number: 20190310077
    Abstract: A DPTSS fiber optic cable includes an optical fiber sheathing cylindrical metal tube accommodating a pressure sensor optical fiber and having a plurality of through holes formed therein; and pressure blocking sections formed at intervals in the axial direction of the cable.
    Type: Application
    Filed: June 8, 2016
    Publication date: October 10, 2019
    Applicant: Neubrex Co., Ltd.
    Inventors: Kinzo Kishida, Yoshiaki Yamauchi, Mitsunori Yokoyama
  • Patent number: 8969920
    Abstract: A vertical semiconductor device in which pinch-off characteristics and breakdown voltage characteristics can be stably improved by fixing the electric potential of a p-type GaN barrier layer with certainty is provided. The semiconductor device includes a GaN-based stacked layer having an opening, a regrown layer including a channel located so as to cover a wall surface of the opening, an n+-type source layer that is in ohmic contact with the source electrode, a p-type GaN barrier layer, and a p+-type GaN-based supplementary layer located between the p-type GaN barrier layer and the n+-type source layer. The p+-type GaN-based supplementary layer and the n+-type source layer form a tunnel junction to fix the electric potential of the p-type GaN barrier layer at a source potential.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: March 3, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Makoto Kiyama, Yu Saitoh, Masaya Okada, Masaki Ueno, Seiji Yaegashi, Kazutaka Inoue, Mitsunori Yokoyama
  • Patent number: 8941174
    Abstract: It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. A GaN-based stacked layer 15 includes n?-type GaN drift layer 4/p-type GaN barrier layer 6/n+-type GaN contact layer 7. An opening 28 extends from a top layer and reaches the n?-type GaN drift layer 4. The semiconductor device includes a regrown layer 27 located so as to cover a wall surface and a bottom portion of the opening, the regrown layer 27 including an electron drift layer 22 and an electron source layer 26, a source electrode S located around the opening, a gate electrode G located on the regrown layer in the opening, and a bottom insulating layer 37 located in the bottom portion of the opening.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: January 27, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masaya Okada, Makoto Kiyama, Yu Saitoh, Seiji Yaegashi, Mitsunori Yokoyama, Kazutaka Inoue
  • Patent number: 8896058
    Abstract: It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. The vertical semiconductor device includes a GaN-based stacked layer 15 having an opening 28 and the GaN-based stacked layer 15 includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. The vertical semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, and a gate electrode G located on the regrown layer. The gate electrode G covers a portion having a length corresponding to the thickness of the p-type GaN-based barrier layer and is terminated at a position on the wall surface, the position being away from the bottom portion of the opening.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: November 25, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masaya Okada, Makoto Kiyama, Yu Saitoh, Seiji Yaegashi, Mitsunori Yokoyama, Kazutaka Inoue
  • Patent number: 8890239
    Abstract: In a vertical semiconductor device including a channel in an opening, a semiconductor device whose high-frequency characteristics can be improved and a method for producing the semiconductor device are provided. The semiconductor device includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. An opening 28 extends from a top layer and reaches the n-type GaN-based drift layer. The semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, a drain electrode D, and a gate electrode G located on the regrown layer. Assuming that the source electrode serving as one electrode and the drain electrode serving as the other electrode constitute a capacitor, the semiconductor device includes a capacitance-decreasing structure that decreases the capacitance of the capacitor.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: November 18, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Yaegashi, Makoto Kiyama, Mitsunori Yokoyama, Kazutaka Inoue, Masaya Okada, Yu Saitoh
  • Patent number: 8816398
    Abstract: There is provided a vertical GaN-based semiconductor device in which the on-resistance can be decreased while the breakdown voltage characteristics are improved using a p-type GaN barrier layer. The semiconductor device includes a regrown layer 27 including a channel located on a wall surface of an opening 28, a p-type barrier layer 6 whose end face is covered, a source layer 7 that is in contact with the p-type barrier layer, a gate electrode G located on the regrown layer, and a source electrode S located around the opening. In the semiconductor device, the source layer has a superlattice structure that is constituted by a stacked layer including a first layer (a layer) having a lattice constant smaller than that of the p-type barrier layer and a second layer (b layer) having a lattice constant larger than that of the first layer.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: August 26, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Makoto Kiyama, Yu Saitoh, Masaya Okada, Seiji Yaegashi, Kazutaka Inoue, Mitsunori Yokoyama
  • Publication number: 20130248876
    Abstract: In a vertical semiconductor device including a channel in an opening, a semiconductor device whose high-frequency characteristics can be improved and a method for producing the semiconductor device are provided. The semiconductor device includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. An opening 28 extends from a top layer and reaches the n-type GaN-based drift layer. The semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, a drain electrode D, and a gate electrode G located on the regrown layer. Assuming that the source electrode serving as one electrode and the drain electrode serving as the other electrode constitute a capacitor, the semiconductor device includes a capacitance-decreasing structure that decreases the capacitance of the capacitor.
    Type: Application
    Filed: July 26, 2011
    Publication date: September 26, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Seiji Yaegashi, Makoto Kiyama, Mitsunori Yokoyama, Kazutaka Inoue, Masaya Okada, Yu Saitoh
  • Publication number: 20130240900
    Abstract: There is provided a semiconductor device or the like which includes a channel and a gate electrode in an opening and in which electric field concentration near a bottom portion of the opening can be reduced. The semiconductor device includes n?-type GaN drift layer 4/p-type GaN barrier layer 6/n+-type GaN contact layer. An opening 28 extends from the top layer and reaches the n-type GaN-based drift layer. The semiconductor device includes a regrown layer 27 located in the opening, the regrown layer 27 including an electron supply layer 26 and an electron drift layer 22, a source electrode S, a drain electrode D, a gate electrode G located on the regrown layer, and a semiconductor impurity adjustment region 31 disposed in the bottom portion of the opening. The impurity adjustment region 31 is a region that promotes a potential drop from the drain electrode side to the gate electrode side in a potential distribution in an off-state.
    Type: Application
    Filed: October 17, 2011
    Publication date: September 19, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Seiji Yaegashi, Makoto Kiyama, Kazutaka Inoue, Mitsunori Yokoyama, Yu Saitoh, Masaya Okada
  • Publication number: 20130234156
    Abstract: It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. A GaN-based stacked layer 15 includes n?-type GaN drift layer 4/p-type GaN barrier layer 6/n+-type GaN contact layer 7. An opening 28 extends from a top layer and reaches the n?-type GaN drift layer 4. The semiconductor device includes a regrown layer 27 located so as to cover a wall surface and a bottom portion of the opening, the regrown layer 27 including an electron drift layer 22 and an electron source layer 26, a source electrode S located around the opening, a gate electrode G located on the regrown layer in the opening, and a bottom insulating layer 37 located in the bottom portion of the opening.
    Type: Application
    Filed: October 17, 2011
    Publication date: September 12, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD
    Inventors: Masaya Okada, Makoto Kiyama, Yu Saitoh, Seiji Yaegashi, Mitsunori Yokoyama, Kazutaka Inoue
  • Publication number: 20130221434
    Abstract: It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. The vertical semiconductor device includes a GaN-based stacked layer 15 having an opening 28 and the GaN-based stacked layer 15 includes n-type GaN-based drift layer 4/p-type GaN-based barrier layer 6/n-type GaN-based contact layer 7. The vertical semiconductor device includes a regrown layer 27 located so as to cover the opening, the regrown layer 27 including an electron drift layer 22 and an electron supply layer 26, a source electrode S, and a gate electrode G located on the regrown layer. The gate electrode G covers a portion having a length corresponding to the thickness of the p-type GaN-based barrier layer and is terminated at a position on the wall surface, the position being away from the bottom portion of the opening.
    Type: Application
    Filed: October 5, 2011
    Publication date: August 29, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Masaya Okada, Makoto Kiyama, Yu Saitoh, Seiji Yaegashi, Mitsunori Yokoyama, Kazutaka Inoue
  • Publication number: 20130181255
    Abstract: There is provided a vertical GaN-based semiconductor device in which the on-resistance can be decreased while the breakdown voltage characteristics are improved using a p-type GaN barrier layer. The semiconductor device includes a regrown layer 27 including a channel located on a wall surface of an opening 28, a p-type barrier layer 6 whose end face is covered, a source layer 7 that is in contact with the p-type barrier layer, a gate electrode G located on the regrown layer, and a source electrode S located around the opening. In the semiconductor device, the source layer has a superlattice structure that is constituted by a stacked layer including a first layer (a layer) having a lattice constant smaller than that of the p-type barrier layer and a second layer (b layer) having a lattice constant larger than that of the first layer.
    Type: Application
    Filed: July 6, 2011
    Publication date: July 18, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Makoto Kiyama, Yu Saitoh, Masaya Okada, Seiji Yaegashi, Kazutaka Inoue, Mitsunori Yokoyama
  • Publication number: 20130168739
    Abstract: A vertical semiconductor device in which pinch-off characteristics and breakdown voltage characteristics can be stably improved by fixing the electric potential of a p-type GaN barrier layer with certainty is provided. The semiconductor device includes a GaN-based stacked layer having an opening, a regrown layer including a channel located so as to cover a wall surface of the opening, an n+-type source layer that is in ohmic contact with the source electrode, a p-type GaN barrier layer, and a p+-type GaN-based supplementary layer located between the p-type GaN barrier layer and the n+-type source layer. The p+-type GaN-based supplementary layer and the n+-type source layer form a tunnel junction to fix the electric potential of the p-type GaN barrier layer at a source potential.
    Type: Application
    Filed: July 6, 2011
    Publication date: July 4, 2013
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Makoto Kiyama, Yu Saitoh, Masaya Okada, Masaki Ueno, Seiji Yaegashi, Kazutaka Inoue, Mitsunori Yokoyama
  • Patent number: 8378388
    Abstract: A semiconductor device includes: a semiconductor layer made of Fe-doped GaN; a first buffer layer that is provided on the semiconductor layer so as to contact an upper surface of the semiconductor layer and is made of AlN or AlxGa1-xN (0.4<x<1); and an operating layer that is provided on the first buffer layer and is made of a GaN-based semiconductor.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: February 19, 2013
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Mitsunori Yokoyama
  • Patent number: 8173464
    Abstract: A method for fabricating a semiconductor device includes growing an AlN layer by MOVPE in which a nitrogen-source flow ratio at a far side from a substrate is set lower than that at a near side, the nitrogen-source flow ratio being a ratio of a flow rate of a nitrogen source to a total flow rate of growth gas; and growing a GaN-based semiconductor layer on the AlN layer by MOVPE.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: May 8, 2012
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Mitsunori Yokoyama
  • Publication number: 20100244098
    Abstract: A semiconductor device includes: a semiconductor layer made of Fe-doped GaN; a first buffer layer that is provided on the semiconductor layer so as to contact an upper surface of the semiconductor layer and is made of AlN or AlxGa1-xN (0.4<x<1); and an operating layer that is provided on the first buffer layer and is made of a GaN-based semiconductor.
    Type: Application
    Filed: March 25, 2010
    Publication date: September 30, 2010
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Mitsunori Yokoyama
  • Publication number: 20100240198
    Abstract: A method for fabricating a semiconductor device includes growing an AlN layer by MOVPE in which a nitrogen-source flow ratio at a far side from a substrate is set lower than that at a near side, the nitrogen-source flow ratio being a ratio of a flow rate of a nitrogen source to a total flow rate of growth gas; and growing a GaN-based semiconductor layer on the AlN layer by MOVPE.
    Type: Application
    Filed: March 19, 2010
    Publication date: September 23, 2010
    Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Mitsunori Yokoyama
  • Publication number: 20090176352
    Abstract: A semiconductor device includes a substrate, a buffer layer that is formed with an aluminum nitride layer on the substrate and has a film thickness of 5 nm to 40 nm, an operating layer that is formed with a gallium nitride-based semiconductor on the buffer layer, and a control electrode that is formed on the operating layer.
    Type: Application
    Filed: March 5, 2009
    Publication date: July 9, 2009
    Applicants: EUDYNA DEVICES, INC., FUJITSU LIMITED
    Inventors: Mitsunori Yokoyama, Kenji Imanishi, Toshihide Kikkawa
  • Publication number: 20060220039
    Abstract: A semiconductor device includes a substrate, a buffer layer that is formed with an aluminum nitride layer on the substrate and has a film thickness of 5 nm to 40 nm, an operating layer that is formed with a gallium nitride-based semiconductor on the buffer layer, and a control electrode that is formed on the operating layer.
    Type: Application
    Filed: March 29, 2006
    Publication date: October 5, 2006
    Applicants: EUDYNA DEVICES INC., FUJITSU LIMITED
    Inventors: Mitsunori Yokoyama, Kenji Imanishi, Toshihide Kikkawa