Patents by Inventor Mitsuo Hayamura

Mitsuo Hayamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7459718
    Abstract: A FET includes a nitride semiconductor in which leak current is reduced and breakdown voltage is improved. The FET is formed from a substrate, a buffer layer made of a nitride semiconductor, a first semiconductor layer made of a nitride semiconductor, and a second semiconductor layer made of a nitride semiconductor, wherein at least the buffer layer and the first semiconductor layer include a p-type dopant. The concentration of the p-type dopant is higher in the buffer layer than that in the first semiconductor layer, and the concentration of the p-type dopant is higher in the first semiconductor layer than that in the second semiconductor layer.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: December 2, 2008
    Assignee: Nichia Corporation
    Inventors: Mitsuo Hayamura, Shiro Akamatsu
  • Publication number: 20060214193
    Abstract: A FET includes a nitride semiconductor in which leak current is reduced and breakdown voltage is improved. The FET is formed from a substrate, a buffer layer made of a nitride semiconductor, a first semiconductor layer made of a nitride semiconductor, and a second semiconductor layer made of a nitride semiconductor, wherein at least the buffer layer and the first semiconductor layer include a p-type dopant. The concentration of the p-type dopant is higher in the buffer layer than that in the first semiconductor layer, and the concentration of the p-type dopant is higher in the first semiconductor layer than that in the second semiconductor layer.
    Type: Application
    Filed: March 22, 2006
    Publication date: September 28, 2006
    Applicant: NICHIA CORPORATION
    Inventors: Mitsuo Hayamura, Shiro Akamatsu