Patents by Inventor Mitsuo Higuchi

Mitsuo Higuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4327466
    Abstract: According to the present invention, a brushing mechanism for brushing an end face of a metal material to be brushed and an angle detector for detecting an inclination of the end face of a metal material to be brushed are rested on a frame mechanism, said frame mechanism is provided in such a manner as to be swingable or fixable with respect to a base, a side surface of said angle detector in parallel to a brushing surface of said brushing mechanism is moved into a space formed between the end face to be brushed and the brushing surface of said brushing mechanism and brought into abutting contact with the face to be brushed, and the frame mechanism is swinged and inclined commensurate to the inclination of the end face to be brushed by the abutment of said angle detector against the face to be brushed, whereby the brushing surface of said brushing mechanism is brought into parallel to the end face to be brushed, so that the brushing of the end face to be brushed by said brushing mechanism can be effected in pa
    Type: Grant
    Filed: April 3, 1980
    Date of Patent: May 4, 1982
    Assignees: Kawasaki Steel Corporation, Aichi Steel Works, Limited
    Inventors: Yoshitsugu Yanagida, Mitsuo Higuchi, Yoshiaki Ito, Shigeru Nakaji, Syogo Ehiro
  • Patent number: 4321489
    Abstract: A voltage detection circuit, for detecting two voltages, that is, a high voltage level and a low voltage level, is disclosed. The voltage detection circuit according to the present invention includes a load element group having a first terminal and a second terminal, and a transistor which is connected between the second terminal of the load element group and ground. The sum of threshold voltages of the load element group has a value higher than the low voltage level to be detected and lower than the high voltage level to be detected. The load element group is kept in an off state when the low voltage level is applied thereto and is kept in on state when the high voltage level is applied thereto.
    Type: Grant
    Filed: July 31, 1979
    Date of Patent: March 23, 1982
    Assignee: Fujitsu Ltd.
    Inventors: Mitsuo Higuchi, Kazuhisa Nakamura, Kohichi Maeda
  • Patent number: 4314360
    Abstract: A semiconductor memory device comprising a memory cell array consisting of a plurality of cell transistors, and additional transistors connected between bit lines and a reference potential point for suppressing the lowering of the potential of a bit line when said semiconductor memory device is changed from a non-operative state to an operative state.
    Type: Grant
    Filed: May 19, 1980
    Date of Patent: February 2, 1982
    Inventors: Mitsuo Higuchi, Kiyoshi Miyasaka
  • Patent number: 4307206
    Abstract: A urea-formaldehyde resin adhesive comprising a powder of a substance having the property of gradually reacting with an acid and thus consuming the acid.
    Type: Grant
    Filed: July 7, 1980
    Date of Patent: December 22, 1981
    Assignees: Oshika Shinko Co., Ltd., Mitsuo Higuchi, Isao Sakata
    Inventors: Mitsuo Higuchi, Isao Sakata
  • Patent number: 4291326
    Abstract: A semiconductor device for use in a bootstrap circuit comprising: first and second MIS field effect transistors connected in series between a power supply line and ground; third and fourth MIS field effect transistors connected in series between the power supply line and ground; a capacitor connected between the gate and source of the third MIS field effect transistor, and; a fifth MIS field effect transistor connected between first and second nodes, the first node connecting the first and second MIS field effect transistors, and the gate of the third MIS transistor, the second node connecting the third and fourth MIS field effect transistors being connected to an output of the device, wherein a p-n junction portion which is connected to the capacitor is protected by a cover for preventing light from penetrating thereinto.
    Type: Grant
    Filed: November 20, 1979
    Date of Patent: September 22, 1981
    Assignee: Fujitsu Limited
    Inventors: Mitsuo Higuchi, Kiyoshi Miyasaka