Abstract: A semiconductor memory device includes a memory match unit configured to check whether memory information identifying the semiconductor memory device matches external memory information supplied from an exterior, a repair match unit configured to check, in response to a finding of a match by the memory match unit, whether an access address matches a repair address indicative of a failed cell position, and a control unit configured to perform a control operation to access a spare memory in response to a finding of a match by the repair match unit.

Abstract: A semiconductor memory apparatus allows accessing data stored therein using a plurality of different addressing types such as bit slice type and word slice type. The semiconductor memory apparatus includes memory elements having a plurality of memory cell arrays and corresponding column gates that control connections between the memory cell arrays and a first sense amp, a first write buffer, a second sense amp, and a second write buffer in response to an external signal designating the addressing type and the reading or writing of data.

Abstract: A semiconductor memory apparatus allows accessing data stored therein using a plurality of different addressing types such as bit slice type and word slice type. The semiconductor memory apparatus includes memory elements having a plurality of memory cell arrays and corresponding column gates that control connections between the memory cell arrays and a first sense amp, a first write buffer, a second sense amp, and a second write buffer in response to an external signal designating the addressing type and the reading or writing of data.

Abstract: A semiconductor integrated circuit apparatus has a basic cell region formed by arranging a plurality of basic cells each including a MOS transistor in longitudinal and transversal directions. The MOS transistor has source-drain section diffusive regions formed on a semiconductor substrate, and a gate electrode formed on a channel region between these source-drain section diffusive regions through a gate insulating film. One portion or all of the channel region of at least one MOS transistor within the basic cell region has an impurity concentration different from that in the channel region of another MOS transistor of the same conductivity type within the same basic cell. For example, a threshold voltage in the channel region of a MOS transistor is increased until about 6 volts by implanting ions into the channel region. No MOS transistor is operated at a power voltage such as 5 volts and separates MOS transistors on both sides thereof from each other.