Patents by Inventor Mitsuo Kimoto
Mitsuo Kimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9177856Abstract: A MOSFET includes: a substrate; a gate insulating film; a gate electrode; an interlayer insulating film formed on the gate insulating film to surround the gate electrode; a buffer film containing Ti and N and containing no Al; and a source electrode containing Ti, Al, and Si. In the MOSFET, a contact hole is formed away from the gate electrode so as to extend through the interlayer insulating film and expose a main surface of the substrate. The buffer film is formed in contact with a side wall surface of the contact hole. The source electrode is formed on and in contact with the buffer film and the main surface of the substrate exposed by forming the contact hole.Type: GrantFiled: April 4, 2013Date of Patent: November 3, 2015Assignees: Sumitomo Electric Industries, Ltd., Renesas Electronics CorporationInventors: Taku Horii, Shinji Kimura, Mitsuo Kimoto
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Publication number: 20140103365Abstract: A semiconductor device includes: a substrate made of silicon carbide; an insulating film formed on a surface of the substrate; a buffer film containing no Al; and an electrode containing Al. The substrate has an electrically conductive region. In the semiconductor device, a contact hole is formed above the electrically conductive region so as to extend through the insulating film and expose the surface of the substrate. The buffer film extends upward on a side wall surface of the contact hole from a bottom surface of the contact hole. The electrode is formed in contact with the electrically conductive region on the bottom surface of the contact hole, and is formed on the insulating film with the buffer film being interposed therebetween.Type: ApplicationFiled: October 11, 2013Publication date: April 17, 2014Applicant: Sumitomo Electric Industries, Ltd.Inventors: Kazunori Fujimoto, Taku Horii, Shinji Kimura, Mitsuo Kimoto
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Publication number: 20130292703Abstract: A MOSFET includes: a substrate; a gate insulating film; a gate electrode; an interlayer insulating film formed on the gate insulating film to surround the gate electrode; a buffer film containing Ti and N and containing no Al; and a source electrode containing Ti, Al, and Si. In the MOSFET, a contact hole is formed away from the gate electrode so as to extend through the interlayer insulating film and expose a main surface of the substrate. The buffer film is formed in contact with a side wall surface of the contact hole. The source electrode is formed on and in contact with the buffer film and the main surface of the substrate exposed by forming the contact hole.Type: ApplicationFiled: April 4, 2013Publication date: November 7, 2013Applicants: Renesas Electronics Corporation, Sumitomo Electric Industries, Ltd.Inventors: Taku HORII, Shinji Kimura, Mitsuo Kimoto
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Patent number: 7566662Abstract: Provided is a method of manufacturing a semiconductor device. After a semiconductor wafer is placed over a wafer stage with which a dry cleaning chamber of a film forming apparatus is equipped, dry cleaning treatment is given over the surface of the semiconductor wafer with a reducing gas. Then, the semiconductor wafer is heat treated at a first temperature of from 100 to 150° C. by using a shower head kept at 180° C. The semiconductor wafer is then vacuum-transferred to a heat treatment chamber, wherein the semiconductor wafer is heat treated at a second temperature of from 150 to 400° C. A product remaining over the main surface of the semiconductor wafer is thus removed. The present invention makes it possible to manufacture a semiconductor device having improved reliability and production yield by reducing variations in the electrical properties of a nickel silicide layer.Type: GrantFiled: April 10, 2007Date of Patent: July 28, 2009Assignee: Renesas Technology Corp.Inventors: Takuya Futase, Hideaki Tsugane, Mitsuo Kimoto, Hidenori Suzuki
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Publication number: 20070238321Abstract: Provided is a method of manufacturing a semiconductor device. After a semiconductor wafer is placed over a wafer stage with which a dry cleaning chamber of a film forming apparatus is equipped, dry cleaning treatment is given over the surface of the semiconductor wafer with a reducing gas. Then, the semiconductor wafer is heat treated at a first temperature of from 100 to 150° C. by using a shower head kept at 180° C. The semiconductor wafer is then vacuum-transferred to a heat treatment chamber, wherein the semiconductor wafer is heat treated at a second temperature of from 150 to 400° C. A product remaining over the main surface of the semiconductor wafer is thus removed. The present invention makes it possible to manufacture a semiconductor device having improved reliability and production yield by reducing variations in the electrical properties of a nickel silicide layer.Type: ApplicationFiled: April 10, 2007Publication date: October 11, 2007Inventors: Takuya Futase, Hideaki Tsugane, Mitsuo Kimoto, Hidenori Suzuki
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Patent number: 6599820Abstract: A method of producing a semiconductor device having a polymetal wiring structure fabricated by a polycrystalline silicon film, a reaction preventing film, and a tungsten film comprising steps of forming a polycrystalline silicon film 4 and a tungsten nitride film 13 on a silicon substrate 1; forming a tungsten film 14 using a target of tungsten containing fluorine of 10 ppm or less by a sputtering method; and forming a gate electrode 15 by patterning a polycrystalline silicon film 4, the tungsten nitride film 13, and the tungsten film 14, whereby a content of fluorine can be reduced, a film separation is prevented, and a preferable transistor property is obtainable.Type: GrantFiled: October 25, 2000Date of Patent: July 29, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuhiro Kanda, Mitsuo Kimoto, Kazuyoshi Maekawa, Noboru Sekiguchi
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Patent number: 6380058Abstract: A barrier layer is formed at a bottom portion, for example, of a through hole. The thickness of the barrier layer at an upper area, for example, of the through hole is made uniform. The method of manufacturing a semiconductor device includes the steps of: forming a barrier layer by sputtering on a main surface of a silicon substrate while maintaining a first distance between a main surface of the target and the main surface of the silicon substrate; and forming a titanium nitride layer by sputtering on and adjacent to a titanium nitride layer by scattering a target material while maintaining a second distance longer than the first distance between the main surface of the target and the main surface of the silicon substrate.Type: GrantFiled: March 8, 1999Date of Patent: April 30, 2002Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Seiji Manabe, Mitsuo Kimoto
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Publication number: 20010046767Abstract: A barrier layer is formed at a bottom portion, for example, of a through hole. The thickness of the barrier layer at an upper area, for example, of the through hole is made uniform. The method of manufacturing a semiconductor device includes the steps of: forming a barrier layer by sputtering on a main surface of a silicon substrate while maintaining a first distance between a main surface of the target and the main surface of the silicon substrate; and forming a titanium nitride layer by sputtering on and adjacent to a titanium nitride layer by scattering a target material while maintaining a second distance longer than the first distance between the main surface of the target and the main surface of the silicon substrate.Type: ApplicationFiled: March 8, 1999Publication date: November 29, 2001Inventors: SEIJI MANABE, MITSUO KIMOTO
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Publication number: 20010037341Abstract: To provide an information providing system which can easily and quickly provide information about suppliers.Type: ApplicationFiled: February 12, 2001Publication date: November 1, 2001Inventors: Mitsuo Kimoto, Sadao Ito, Yoshihide Nanbu, Takanori Yokoi, Naka Ito, Ikuo Fuchi, Kazuyuki Tandai, Hitoshi Tomita, Atsushi Takasawa, Mitsuo Suita, Hirofumi Sato, Shogo Mihara, Atsushi Matsunawa, Nobu Matsui, Tsugunao Kobayashi
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Patent number: 6304001Abstract: The semiconductor device with the alignment mark includes a convex portion as a film growth control region for forming side surfaces approximately parallel to sidewalls on surfaces opposite to the sidewalls of first metal interconnection layer formed in a recess portion of the alignment mark at the time of deposition of first metal interconnection layer. Thus, the semiconductor device with the alignment mark and manufacturing method thereof allowing the easy and accurate detection of the location of a layer deposited on side surfaces of the alignment mark can be provided.Type: GrantFiled: March 29, 1999Date of Patent: October 16, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Noboru Sekiguchi, Kimio Hagi, Mitsuo Kimoto