Patents by Inventor Mitsuo Kimoto

Mitsuo Kimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9177856
    Abstract: A MOSFET includes: a substrate; a gate insulating film; a gate electrode; an interlayer insulating film formed on the gate insulating film to surround the gate electrode; a buffer film containing Ti and N and containing no Al; and a source electrode containing Ti, Al, and Si. In the MOSFET, a contact hole is formed away from the gate electrode so as to extend through the interlayer insulating film and expose a main surface of the substrate. The buffer film is formed in contact with a side wall surface of the contact hole. The source electrode is formed on and in contact with the buffer film and the main surface of the substrate exposed by forming the contact hole.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: November 3, 2015
    Assignees: Sumitomo Electric Industries, Ltd., Renesas Electronics Corporation
    Inventors: Taku Horii, Shinji Kimura, Mitsuo Kimoto
  • Publication number: 20140103365
    Abstract: A semiconductor device includes: a substrate made of silicon carbide; an insulating film formed on a surface of the substrate; a buffer film containing no Al; and an electrode containing Al. The substrate has an electrically conductive region. In the semiconductor device, a contact hole is formed above the electrically conductive region so as to extend through the insulating film and expose the surface of the substrate. The buffer film extends upward on a side wall surface of the contact hole from a bottom surface of the contact hole. The electrode is formed in contact with the electrically conductive region on the bottom surface of the contact hole, and is formed on the insulating film with the buffer film being interposed therebetween.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 17, 2014
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Kazunori Fujimoto, Taku Horii, Shinji Kimura, Mitsuo Kimoto
  • Publication number: 20130292703
    Abstract: A MOSFET includes: a substrate; a gate insulating film; a gate electrode; an interlayer insulating film formed on the gate insulating film to surround the gate electrode; a buffer film containing Ti and N and containing no Al; and a source electrode containing Ti, Al, and Si. In the MOSFET, a contact hole is formed away from the gate electrode so as to extend through the interlayer insulating film and expose a main surface of the substrate. The buffer film is formed in contact with a side wall surface of the contact hole. The source electrode is formed on and in contact with the buffer film and the main surface of the substrate exposed by forming the contact hole.
    Type: Application
    Filed: April 4, 2013
    Publication date: November 7, 2013
    Applicants: Renesas Electronics Corporation, Sumitomo Electric Industries, Ltd.
    Inventors: Taku HORII, Shinji Kimura, Mitsuo Kimoto
  • Patent number: 7566662
    Abstract: Provided is a method of manufacturing a semiconductor device. After a semiconductor wafer is placed over a wafer stage with which a dry cleaning chamber of a film forming apparatus is equipped, dry cleaning treatment is given over the surface of the semiconductor wafer with a reducing gas. Then, the semiconductor wafer is heat treated at a first temperature of from 100 to 150° C. by using a shower head kept at 180° C. The semiconductor wafer is then vacuum-transferred to a heat treatment chamber, wherein the semiconductor wafer is heat treated at a second temperature of from 150 to 400° C. A product remaining over the main surface of the semiconductor wafer is thus removed. The present invention makes it possible to manufacture a semiconductor device having improved reliability and production yield by reducing variations in the electrical properties of a nickel silicide layer.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: July 28, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Takuya Futase, Hideaki Tsugane, Mitsuo Kimoto, Hidenori Suzuki
  • Publication number: 20070238321
    Abstract: Provided is a method of manufacturing a semiconductor device. After a semiconductor wafer is placed over a wafer stage with which a dry cleaning chamber of a film forming apparatus is equipped, dry cleaning treatment is given over the surface of the semiconductor wafer with a reducing gas. Then, the semiconductor wafer is heat treated at a first temperature of from 100 to 150° C. by using a shower head kept at 180° C. The semiconductor wafer is then vacuum-transferred to a heat treatment chamber, wherein the semiconductor wafer is heat treated at a second temperature of from 150 to 400° C. A product remaining over the main surface of the semiconductor wafer is thus removed. The present invention makes it possible to manufacture a semiconductor device having improved reliability and production yield by reducing variations in the electrical properties of a nickel silicide layer.
    Type: Application
    Filed: April 10, 2007
    Publication date: October 11, 2007
    Inventors: Takuya Futase, Hideaki Tsugane, Mitsuo Kimoto, Hidenori Suzuki
  • Patent number: 6599820
    Abstract: A method of producing a semiconductor device having a polymetal wiring structure fabricated by a polycrystalline silicon film, a reaction preventing film, and a tungsten film comprising steps of forming a polycrystalline silicon film 4 and a tungsten nitride film 13 on a silicon substrate 1; forming a tungsten film 14 using a target of tungsten containing fluorine of 10 ppm or less by a sputtering method; and forming a gate electrode 15 by patterning a polycrystalline silicon film 4, the tungsten nitride film 13, and the tungsten film 14, whereby a content of fluorine can be reduced, a film separation is prevented, and a preferable transistor property is obtainable.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: July 29, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuhiro Kanda, Mitsuo Kimoto, Kazuyoshi Maekawa, Noboru Sekiguchi
  • Patent number: 6380058
    Abstract: A barrier layer is formed at a bottom portion, for example, of a through hole. The thickness of the barrier layer at an upper area, for example, of the through hole is made uniform. The method of manufacturing a semiconductor device includes the steps of: forming a barrier layer by sputtering on a main surface of a silicon substrate while maintaining a first distance between a main surface of the target and the main surface of the silicon substrate; and forming a titanium nitride layer by sputtering on and adjacent to a titanium nitride layer by scattering a target material while maintaining a second distance longer than the first distance between the main surface of the target and the main surface of the silicon substrate.
    Type: Grant
    Filed: March 8, 1999
    Date of Patent: April 30, 2002
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Seiji Manabe, Mitsuo Kimoto
  • Publication number: 20010046767
    Abstract: A barrier layer is formed at a bottom portion, for example, of a through hole. The thickness of the barrier layer at an upper area, for example, of the through hole is made uniform. The method of manufacturing a semiconductor device includes the steps of: forming a barrier layer by sputtering on a main surface of a silicon substrate while maintaining a first distance between a main surface of the target and the main surface of the silicon substrate; and forming a titanium nitride layer by sputtering on and adjacent to a titanium nitride layer by scattering a target material while maintaining a second distance longer than the first distance between the main surface of the target and the main surface of the silicon substrate.
    Type: Application
    Filed: March 8, 1999
    Publication date: November 29, 2001
    Inventors: SEIJI MANABE, MITSUO KIMOTO
  • Publication number: 20010037341
    Abstract: To provide an information providing system which can easily and quickly provide information about suppliers.
    Type: Application
    Filed: February 12, 2001
    Publication date: November 1, 2001
    Inventors: Mitsuo Kimoto, Sadao Ito, Yoshihide Nanbu, Takanori Yokoi, Naka Ito, Ikuo Fuchi, Kazuyuki Tandai, Hitoshi Tomita, Atsushi Takasawa, Mitsuo Suita, Hirofumi Sato, Shogo Mihara, Atsushi Matsunawa, Nobu Matsui, Tsugunao Kobayashi
  • Patent number: 6304001
    Abstract: The semiconductor device with the alignment mark includes a convex portion as a film growth control region for forming side surfaces approximately parallel to sidewalls on surfaces opposite to the sidewalls of first metal interconnection layer formed in a recess portion of the alignment mark at the time of deposition of first metal interconnection layer. Thus, the semiconductor device with the alignment mark and manufacturing method thereof allowing the easy and accurate detection of the location of a layer deposited on side surfaces of the alignment mark can be provided.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: October 16, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Noboru Sekiguchi, Kimio Hagi, Mitsuo Kimoto