Patents by Inventor Mitsuo Kono

Mitsuo Kono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5866468
    Abstract: In the wafer-bonding method of fabricating an SOI (silicon-on-insulator) substrate, even if there exists thickness variation in the silicon layer, devices fabricated onto the silicon layer, in accordance with the present invention, have a decreased threshold voltage variation. According to the present invention, after bonding two wafers, the thickness of the thinned silicon layer atop the SOI substrate is measured to precisely determine the local thickness distribution. However, the fabricated devices' threshold voltage depends upon the doping concentration as well as the thickness of the silicon layer. Shielding masks of photoresist are thereafter formed selectively on a portion of the silicon that are thicker. Then, through the masks as shielding, impurities are implanted into the silicon layer to adjust the doping concentration therein. Accordingly, the doping concentration is varied corresponding to the thickness, with the result that the threshold voltage variation nearly approaches zero.
    Type: Grant
    Filed: August 14, 1996
    Date of Patent: February 2, 1999
    Assignee: Komatsu Electronic Metal Co., Ltd.
    Inventors: Mitsuo Kono, Kei Matsumoto
  • Patent number: 5708365
    Abstract: A simple method for evaluating the dielectric breakdown of an oxide layer on a silicon wafer is disclosed. The SPV method is utilized to measure a diffusion length L.sub.on of minority carriers when the silicon wafer is illuminated by white light from another source and a diffusion length L.sub.off of the minority carriers when the silicon wafer is not illuminated by white light from another source. A diffusion length L.sub.safe, which is determined by trap sites in the silicon wafer, is calculated from an equation L.sub.safe =(L.sub.off.sup.-2 -L.sub.on.sup.-2).sup.-1/2. Since L.sub.safe has a strong correlation with the dielectric breakdown of the oxide layer, the dielectric breakdown of the oxide layer can be easily evaluated by L.sub.safe during the fabrication of the silicon wafer.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: January 13, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Shiro Yoshino, Seiichi Shimura, Mitsuo Kono
  • Patent number: 5679476
    Abstract: An epitaxial wafer capable of removing impurities and oxide layers thereon having a high dielectric strength is disclosed. A substrate wafer 1 in which laser-scattering centers have a density of higher than 5.times.10.sup.6 /cm.sup.3 is provided. An epitaxial layer 3 is formed by epitaxial growth on a completely clean surface of the substrate. The surface of the epitaxial layer consists of a non-defect layer which is provided for device active regions. Moreover, a high density of laser-scattering centers are distributed near the interface of the epitaxial layer and the substrate wafer and the interior of the substrate, thus providing for a wafer capable of removing impurities.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: October 21, 1997
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Noriyuki Uemura, Mitsuo Kono
  • Patent number: 5506154
    Abstract: In manufacturing a semiconductor device, when a SORI limit value of a silicon single crystal wafer to be material in manufacturing devices, and a bulk micro defect density are defined in fixed ranges for said wafer, as required by the device yield and the gettering capability, said wafer having an initial oxygen concentration capable of simultaneously satisfying said fixed ranges is subject to a preheat treatment for the formation of an oxygen precipitate nucleus by using a time capable of simultaneously satisifying a fixed range between the upper and lower limit values of said initial oxygen concentration and the fixed range of said bulk micro defect density. Use of the process of the present invention will make it possible that the SORI of a wafer is limited to its lowest extent, and a combination of a variety of conditions for insuring the BMD density required for exertion of a desired gettering capability is efficiently chosen in a short period of time without relying upon trial and error.
    Type: Grant
    Filed: July 9, 1993
    Date of Patent: April 9, 1996
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hiroyuki Kawahara, Mitsuo Kono
  • Patent number: 4086463
    Abstract: A flux-cored wire for electrogas arc welding includes a sheath of steel hoop made of material selected from a group of materials consisting of mild steel and stainless steel. A flux is provided internally within the coating. The flux contains CaF.sub.2, Fe--Si, SiO.sub.2, CaCO.sub.3, Cr and Mn. The flux may also contain Fe, Fe--Nb, Me--Mo and/or Me--Cu.
    Type: Grant
    Filed: January 26, 1976
    Date of Patent: April 25, 1978
    Assignee: Tsukishima Kikai Co., Ltd.
    Inventors: Jimpei Omori, Mitsuo Kono, Torataro Takeuchi, Noboru Oikawa