Abstract: A dual data processing system comprising a first data processing unit having a first control unit and a first logic switching circuit; a second control unit having a second logic switching circuit; a pair of switch circuits coupled to the first and second logic switching circuits, respectively; adapter buffers to be coupled selectively to the first and second control units according to the operation of the switch circuits; a first power source for supplying electric power to the first control unit and the adapter buffers coupled thereto; and a second power source for supplying electric power to the second control unit and the adapter buffers coupled thereto. The switch circuits are operated to connect the adapter buffers selectively to the first and second control units so that load balance is kept between the first and second control units.