Patents by Inventor Mitsuo Morihisa

Mitsuo Morihisa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4567575
    Abstract: An interface circuit is disposed between an NMOS random access memory and a PMOS central processor unit in order to ensure accurate data transfer therebetween. The interface circuit includes a pull-up system for pulling up a signal transmission line to a desired voltage level. The pull-up system is energized when the data signal is transferred from the NMOS random access memory into the PMOS central processor unit. The pull-up operation is not conducted when the data signal is transferred from the PMOS central processor unit into the NMOS random access memory.
    Type: Grant
    Filed: April 26, 1985
    Date of Patent: January 28, 1986
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Mitsuo Morihisa, Hideyuki Akao
  • Patent number: 4399524
    Abstract: A memory protection system includes an auxiliary power supply source for maintaining information stored in a random access memory when the main power supply is terminated. When the main power supply voltage level becomes lower than a preselected level, a detection unit develops a control signal for applying a disabling signal to a chip selection terminal included in the random access memory, whereby a load such as a central processor unit connected to the random access memory is electrically disconnected from the random access memory to minimize the power dissipation.
    Type: Grant
    Filed: February 18, 1981
    Date of Patent: August 16, 1983
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Norio Muguruma, Mitsuo Morihisa, Hideyuki Akao
  • Patent number: 4351021
    Abstract: A power supply circuit includes a rectifier for converting an alternating voltage to a DC voltage for driving a single chip LSI microcomputer control system in, for example, a microwave oven. A switching circuit is included in the power supply circuit for developing an output DC voltage only after the DC voltage derived from the rectifier reaches a preselected level. The switching circuit includes large current transistors connected in the Darlington fashion, whereby the power supply circuit develops the output DC voltage with a short leading transient period which is required for developing an auto-clear signal in the single chip LSI microcomputer control system.
    Type: Grant
    Filed: February 18, 1981
    Date of Patent: September 21, 1982
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Mitsuo Morihisa, Tadao Inoue
  • Patent number: 4322694
    Abstract: In a crystal oscillator for solid state wristwatches, the input of an impedance converter is connected to the output of a complementarily connected transistor amplifier which performs linear operation within its essential operating range, to thereby stabilize and decrease the output impedance of the amplifier on the average. The impedance converter includes one or more active elements such as MOSFET's, junction type FET's and bipolar transistors. A quartz resonator is connected between the input of the complementarily connected transistor amplifier and the output of the impedance converter.
    Type: Grant
    Filed: July 16, 1979
    Date of Patent: March 30, 1982
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Mitsuo Morihisa
  • Patent number: 4279010
    Abstract: A DC-DC converter for supplying a sufficient power voltage for solid state watches includes field-effect mode transistors operatively associated with charging and discharging paths of multi-stage capacitors which are primary components of the DC-DC voltage converter. The field-effect mode transistors are responsive to outputs from a level converter which in turn converts its input voltage to charge voltage at the last stage capacitor in response to enable signals. During the initial status of operation, the field effect mode switching transistors and the level converter are driven via the parasitic diodes of the field effect mode transistors, P-N junction type diodes provided for protecting the parasitic diodes from damage, or P-N junction type diodes provided exclusively for initiating purposes.
    Type: Grant
    Filed: May 12, 1978
    Date of Patent: July 14, 1981
    Inventor: Mitsuo Morihisa
  • Patent number: 4128993
    Abstract: Zero adjustment of second information in an electronic timepiece is carried out upon receiving a command from the operator. "Increment one" is performed upon minute information when the second information is between 24 and 59 seconds when the zero adjustment command is generated. Minute information is not changed when the second information is between 0 and 23 seconds when the zero adjustment command is generated.
    Type: Grant
    Filed: August 15, 1975
    Date of Patent: December 12, 1978
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hidetoshi Maeda, Mitsuo Morihisa, Takehiko Sasaki
  • Patent number: 4091338
    Abstract: In a crystal oscillator for solid state wristwatches, the input of an impedance converter is connected to the output of a complementarily connected transistor amplifier which performs linear operation within its essential operating range, thereby stabilizing and decreasing output impedance of the amplifier on the average. The impedance converter includes one or more active elements such as MOSFET's, junction type FET's and bipolar transistors. A quartz oscillator is connected between the input of the complementarily connected transistor amplifier and the output of the output impedance converter.
    Type: Grant
    Filed: January 19, 1977
    Date of Patent: May 23, 1978
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Mitsuo Morihisa