Abstract: A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.

Abstract: A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.

Abstract: A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.

Abstract: A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.

Abstract: A first transistor includes a first gate insulating film, a first gate electrode, and a first sidewall. A second transistor includes a second gate insulating film, a second gate electrode, and a second sidewall. A capacitive element is connected to one side of source and drain regions of the second transistor. The first gate insulating film has the same thickness as that of the second gate insulating film, and the first gate electrode has the same thickness of that of the second gate electrode. The width of the second sidewall is larger than the width of the first sidewall.

Abstract: A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.

Abstract: A first transistor includes a first gate insulating film, a first gate electrode, and a first sidewall. A second transistor includes a second gate insulating film, a second gate electrode, and a second sidewall. A capacitive element is connected to one side of source and drain regions of the second transistor. The first gate insulating film has the same thickness as that of the second gate insulating film, and the first gate electrode has the same thickness of that of the second gate electrode. The width of the second sidewall is larger than the width of the first sidewall.

Abstract: A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.

Abstract: A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.

Abstract: A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.

Abstract: A semiconductor device includes an N-type semiconductor region formed in a semiconductor substrate; a p-type semiconductor region formed in a region deeper in the semiconductor substrate than the N-type semiconductor region; and a heavy metal capturing region formed in a portion of the p-type semiconductor region to capture heavy metal ions. The heavy metal capturing region may be a P-type region. It is preferable that the diffusion speed of the heavy metal ions is slower in the heavy metal capturing region than in the p-type semiconductor region.

Abstract: A semiconductor device is disclosed that can include a gate electrode (6) having a lower layer (6a) and a higher layer (6b), a mask insulating film (7) formed over a higher layer (6b). A side surface insulating film (9) may be formed on sides of a gate electrode (6) and a side wall insulating film (8) may be formed on the sides of a gate electrode (6) and mask insulating film (7). A low density impurity region (3) may be formed with a gate electrode (6) and side surface insulating film (9) as a mask. A higher density impurity region (4) may be formed with a gate electrode (6) and side wall insulating film (8) as a mask. A contact plug (10) may be formed between side wall insulating films (8) that contacts a higher density impurity region (4). A gate electrode (6) may have a reverse tapered shape when viewed in cross section. A lower layer (6a) may have a reverse tapered shape and/or a side surface insulating film (9) may have a greater thickness on sides of a higher layer (6b) than on a lower layer (6a).

Abstract: A semiconductor device is disclosed that can include a gate electrode (6) having a lower layer (6a) and a higher layer (6b), a mask insulating film (7) formed over a higher layer (6b). A side surface insulating film (9) may be formed on sides of a gate electrode (6) and a side wall insulating film (8) may be formed on the sides of a gate electrode (6) and mask insulating film (7). A low density impurity region (3) may be formed with a gate electrode (6) and side surface insulating film (9) as a mask. A higher density impurity region (4) may be formed with a gate electrode (6) and side wall insulating film (8) as a mask. A contact plug (10) may be formed between side wall insulating films (8) that contacts a higher density impurity region (4). A gate electrode (6) may have a reverse tapered shape when viewed in cross section. A lower layer (6a) may have a reverse tapered shape and/or a side surface insulating film (9) may have a greater thickness on sides of a higher layer (6b) than on a lower layer (6a).