Patents by Inventor Mitsuo Sano

Mitsuo Sano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11901185
    Abstract: According to an embodiment, an etching method includes forming a first layer on a substrate having a main surface including first and second regions adjacent to each other, the first layer including a portion covering the first region and having a plurality of openings or one or more openings defining a plurality of island-shaped portions, and the first layer further including a portion as a continuous layer covering the second region, forming a catalyst layer an a portion(s) of the main surface exposed in the openings by plating, forming a second layer to cover a portion of the catalyst layer adjacent to a boundary between the first and second regions and expose a portion of the catalyst layer spaced apart from the boundary, and etching the substrate in a presence of the catalyst layer and the second layer.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: February 13, 2024
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuo Sano, Susumu Obata, Kazuhito Higuchi, Takayuki Tajima
  • Patent number: 11862667
    Abstract: According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, and a dielectric layer. The conductive substrate has a first main surface and a second main surface and is provided with a plurality of recesses on the first main surface. The conductive substrate is further provided with a plurality of holes in one or more portions each sandwiched between two adjacent ones of the recesses such that a region on a side of the first main surface has a larger porosity than a region on a side of the second main surface. The conductive layer covers the first main surface, side walls and bottom surfaces of the recesses, and walls of the holes. The dielectric layer is interposed between the conductive substrate and the conductive layer.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: January 2, 2024
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Susumu Obata, Keiichiro Matsuo, Mitsuo Sano, Kazuhito Higuchi, Kazuo Shimokawa
  • Publication number: 20230307184
    Abstract: According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer therebetween, and first and second internal electrodes. The substrate has first and second main surfaces. One partial region of the first main surface is provided with first recesses. A region of the second surface corresponding to a combination of the one partial region and another partial region is provided with second recesses. The conductive layer covers the main surfaces and side walls and bottom surfaces of the recesses. The first internal electrode is provided on the one partial region and electrically connected to the conductive layer. The second internal electrode is provided on the another partial region and electrically connected to the substrate.
    Type: Application
    Filed: May 10, 2023
    Publication date: September 28, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhito HIGUCHI, Kazuo SHIMOKAWA, Susumu OBATA, Mitsuo SANO
  • Publication number: 20230298907
    Abstract: In general, according to one embodiment, there is provided a method of manufacturing a structure. The method includes forming a recess in a semiconductor substrate; oxidizing at least a bottom inner surface of the recess; and providing at least the bottom inner surface of the recess with a liquid capable of dissolving an oxide of a semiconductor substrate material.
    Type: Application
    Filed: March 14, 2023
    Publication date: September 21, 2023
    Inventors: Mitsuo Sano, Susumu Obata, Kazuhito Higuchi, Takayuki Tajima
  • Patent number: 11688557
    Abstract: According to an embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer therebetween, and first and second internal electrodes. The substrate has first and second main surfaces. One partial region of the first main surface is provided with first recesses. A region of the second surface corresponding to a combination of the one partial region and another partial region is provided with second recesses. The conductive layer covers the main surfaces and side walls and bottom surfaces of the recesses. The first internal electrode is provided on the one partial region and electrically connected to the conductive layer. The second internal electrode is provided on the another partial region and electrically connected to the substrate.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: June 27, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhito Higuchi, Kazuo Shimokawa, Susumu Obata, Mitsuo Sano
  • Patent number: 11678837
    Abstract: The objective of the present invention is to provide a hardness meter which estimates hardness in a stable manner regardless of a compression strength. A hardness meter includes: a movable portion which is continuously pressed against an object to be measured; a sensor which outputs an output signal reflecting a reaction force at a part of the object to be measured; a motive force mechanism that causes the movable portion to perform a piston motion; a hardness estimating portion which estimates the hardness of the object on the basis of an alternating current component of the output signal, generated by the piston motion; a position estimating portion which estimates a measurement position information by shooting with a camera; and a hardness map display portion which maps and displays the hardness on a schematic diagram of the surface of a living body based on the measurement position information.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: June 20, 2023
    Assignee: Maxell, Ltd.
    Inventors: Yuko Sano, Akihiko Kandori, Mitsuo Okimoto, Shigemitsu Ando, Mitsunobu Watanabe
  • Publication number: 20230091900
    Abstract: According to one embodiment, an etching apparatus includes a first container including an opening covered by a semiconductor substrate; a second container including an opening covered by a catalyst layer; a first flow path configured to communicate with the first container; a second flow path configured to communicate with the second container; a cation exchange film interposed between the first flow path and the second flow path and allowing at least protons to pass through; and an electric field applier configured to apply an electric field to the semiconductor substrate.
    Type: Application
    Filed: March 16, 2022
    Publication date: March 23, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takayuki TAJIMA, Kazuhito HIGUCHI, Susumu OBATA, Mitsuo SANO
  • Publication number: 20230077915
    Abstract: According to one embodiment, an etching method includes etching a surface made of a semiconductor and having a catalyst layer formed on the surface, by an etching agent in contact with the surface. The catalyst layer contains noble metal. The etching agent contains an oxidizer, a corrosive agent, and a N-containing polymer agent.
    Type: Application
    Filed: March 15, 2022
    Publication date: March 16, 2023
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuo SANO, Susumu OBATA, Kazuhito HIGUCHI, Takayuki TAJIMA
  • Patent number: 11588059
    Abstract: A structural body according to an embodiment includes a conductive substrate. A main surface of the conductive substrate includes a first region and a second region adjacent to the first region and lower in height than the first region. The first region is provided with one or more recesses having a bottom, a position of which is lower than a position of the second region. A surface region of the conductive substrate on a side of the main surface includes a porous structure at a position between the second region and the one or more recesses.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: February 21, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuo Sano, Susumu Obata, Kazuhito Higuchi, Kazuo Shimokawa
  • Patent number: 11551864
    Abstract: According to one embodiment, a capacitor includes a conductive substrate, a conductive layer, a dielectric layer, and first and second external electrodes. The conductive substrate has a first main surface provided with recess(s), a second main surface, and an end face extending between edges of the first and second main surfaces. The conductive layer covers the first main surface and side walls and bottom surfaces of the recess(s). The dielectric layer is interposed between the conductive substrate and the conductive layer. The first external electrode includes a first electrode portion facing the end face and is electrically connected to the conductive layer. The second external electrode includes a second electrode portion facing the end face and is electrically connected to the conductive substrate.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: January 10, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiichiro Matsuo, Susumu Obata, Mitsuo Sano, Kazuhito Higuchi, Kazuo Shimokawa
  • Patent number: 11508525
    Abstract: A capacitor according to an embodiment includes a substrate having a first surface and a second surface and provided with one or more first through holes each extending from the first surface to the second surface, a first conductive layer covering the first surface, the second surface, and side walls of the one or more first through holes, a second conductive layer facing the first surface, the second surface, and the side walls of the one or more first through holes, with the first conductive layer interposed therebetween, and a dielectric layer interposed between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: November 22, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhito Higuchi, Susumu Obata, Keiichiro Matsuo, Mitsuo Sano
  • Publication number: 20220310582
    Abstract: According to an embodiment, a semiconductor device includes a layer stack including a conductive substrate containing semiconductor material and including a first main surface provided with one or more recesses and a second main surface opposite to the first main surface, a conductive layer covering at least part of the first main surface and side walls and bottom surfaces of the one or more recesses, and a dielectric layer interposed between the conductive substrate and the conductive layer, the conductive layer and a portion of the conductive substrate adjacent to the dielectric layer being an upper electrode and a lower electrode of a capacitor, respectively, an insulating layer provided on the capacitor or on the second main surface, and an inductor provided on the insulating layer at a position of the capacitor.
    Type: Application
    Filed: September 13, 2021
    Publication date: September 29, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Susumu OBATA, Kazuhito HIGUCHI, Mitsuo SANO, Takayuki TAJIMA
  • Publication number: 20220301877
    Abstract: According to an embodiment, an etching method includes forming a first layer on a substrate having a main surface including first and second regions adjacent to each other, the first layer including a portion covering the first region and having a plurality of openings or one or more openings defining a plurality of island-shaped portions, and the first layer further including a portion as a continuous layer covering the second region, forming a catalyst layer an a portion(s) of the main surface exposed in the openings by plating, forming a second layer to cover a portion of the catalyst layer adjacent to a boundary between the first and second regions and expose a portion of the catalyst layer spaced apart from the boundary, and etching the substrate in a presence of the catalyst layer and the second layer.
    Type: Application
    Filed: September 13, 2021
    Publication date: September 22, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuo SANO, Susumu OBATA, Kazuhito HIGUCHI, Takayuki TAJIMA
  • Publication number: 20220279780
    Abstract: In order that an agriculturally active ingredient, particularly a water-insoluble or water-hardly soluble agriculturally active ingredient sufficiently exerts its effects, it is used preferably in the form of an agricultural formulation having the agriculturally active ingredient dissolved, particularly a clear agricultural formulation having not only the agriculturally active ingredient but also other components contained in the agricultural formulation dissolved. When the agricultural formulation is practically used, if foaming when diluted with water is intense, foam may overflow from a tank in which the solution is prepared. A clear agricultural formulation having the agriculturally active ingredient dissolved and further other components contained in the agricultural formulation dissolved, and its foaming when diluted with water suppressed, is required.
    Type: Application
    Filed: July 27, 2020
    Publication date: September 8, 2022
    Applicant: ISHIHARA SANGYO KAISHA, LTD.
    Inventors: Mitsuo SANO, Takao AWAZU, Takashi OKADA, Yutaka ISHIBASHI, Yusuke KOBAYASHI
  • Patent number: 11411074
    Abstract: According to an embodiment, a structure includes a substrate including a semiconductor material, wherein the substrate is provided with one or more recesses each of which has a depth direction that is equal to a thickness direction of the substrate, and the one or more recesses include a sidewall on which a plurality of grooves each extending in the depth direction are provided.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: August 9, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuo Sano, Susumu Obata, Kazuhito Higuchi
  • Patent number: 11322308
    Abstract: According to an embodiment, a capacitor includes a conductive substrate, a conductive layer and a dielectric layer. The conductive substrate has a first main surface and a second main surface. The first main surface includes sub-regions. Each sub-region is provided with recesses or projections each having a shape extending in one direction and arranged in a width direction thereof. One or more of the sub-regions and another one or more of the sub-regions are different from each other in a length direction of the recesses or protrusions. The conductive layer covers sidewalls and bottom surfaces of the recesses or sidewalls and top surfaces of the projections. The dielectric layer is interposed between the conductive substrate and the conductive layer.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: May 3, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuo Sano, Susumu Obata, Kazuhito Higuchi, Kazuo Shimokawa
  • Publication number: 20220115238
    Abstract: According to an embodiment, an etching method includes forming an uneven structure including a protruding portion on a surface of a semiconductor substrate, the protruding portion having a reverse tapered cross-sectional shape; forming a catalyst layer on the surface of the semiconductor substrate at a top surface of the protruding portion, the catalyst layer including a noble metal; and supplying an etching solution to the catalyst layer to etch the semiconductor substrate with an assist from the noble metal as a catalyst.
    Type: Application
    Filed: June 24, 2021
    Publication date: April 14, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takayuki TAJIMA, Kazuhito HIGUCHI, Susumu OBATA, Mitsuo SANO
  • Publication number: 20210407867
    Abstract: A semiconductor wafer includes a surface having at least one recess including an inner wall surface. The inner wall surface is exposed.
    Type: Application
    Filed: September 7, 2021
    Publication date: December 30, 2021
    Applicants: KABUSHIKI KAISHA TOSHIBA, Kioxia Corporation
    Inventors: Fuyuma ITO, Yasuhito YOSHIMIZU, Nobuhito KUGE, Yui KAGI, Susumu OBATA, Keiichiro MATSUO, Mitsuo SANO
  • Publication number: 20210299648
    Abstract: According to an embodiment, a method of forming a catalyst layer includes performing displacement plating on a substrate having a surface that is made of a semiconductor and includes a plurality of projections, thereby depositing a catalytic metal at positions of the plurality of projections.
    Type: Application
    Filed: March 15, 2021
    Publication date: September 30, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Susumu OBATA, Mitsuo SANO, Keiichiro MATSUO, Kazuhito HIGUCHI, Kazuo SHIMOKAWA
  • Publication number: 20210296513
    Abstract: A structural body according to an embodiment includes a conductive substrate. A main surface of the conductive substrate includes a first region and a second region adjacent to the first region and lower in height than the first region. The first region is provided with one or more recesses having a bottom, a position of which is lower than a position of the second region. A surface region of the conductive substrate on a side of the main surface includes a porous structure at a position between the second region and the one or more recesses.
    Type: Application
    Filed: March 15, 2021
    Publication date: September 23, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuo SANO, Susumu OBATA, Kazuhito HIGUCHI, Kazuo SHIMOKAWA