Patents by Inventor Mitsuo Sugino
Mitsuo Sugino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150338174Abstract: A heat transfer sheet of the present invention includes a heat transfer layer having a first portion and a second portion provided in a position different from the first portion in a planar view of the heat transfer layer, the second portion being capable of expanding and contracting in a thickness direction of the heat transfer layer at an expansion ratio larger than that of the first portion depending on temperature changes in an object from which heat is to be dissipated.Type: ApplicationFiled: July 31, 2015Publication date: November 26, 2015Applicants: SUMITOMO BAKELITE COMPANY LIMITED, TOYOTA TSUSHO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashi MURATA, Yoshiyuki NAKAMURA, Izumi TAKAHASHI, Hatsuhiro SOH, Kazumoto SHIMIZU, Yoshihide NII, Shinichiro ITO, Hitoshi KAWAGUCHI, Mitsuo SUGINO
-
Patent number: 8704378Abstract: A semiconductor device 1 is equipped with a first substrate 3 on which a first semiconductor chip 2 is mounted, a second substrate 5 on which a second semiconductor chip 4 is mounted, and connecting sections 6 that electrically connect the first substrate 3 and the second substrate 5. The first substrate 3 has build-up layers 31A and 31B in each of which an insulating layer 311 containing a resin and conductor interconnect layers 312 and 313 are laminated alternately, and the respective conductor interconnect layers 312 are connected by a conductive layer 314 provided in via holes of the insulating layers 311. The second substrate 5 also has build-up layers 31A and 31B.Type: GrantFiled: May 15, 2007Date of Patent: April 22, 2014Assignee: Sumitomo Bakelite Co., Ltd.Inventors: Mitsuo Sugino, Satoru Katsurayama, Hiroyuki Yamashita
-
Patent number: 8629556Abstract: The semiconductor device 1 includes a substrate 3, a semiconductor chip 4 mounted on the substrate 3, the substrate 3, a bump 5 connecting the substrate 3 and the semiconductor chip 4, and an underfill 6 filling in around the bump 5. In the case of a bump 5 composed of a high-melting-point solder having a melting point of 230° C. or more, the underfill 6 is composed of a resin material having an elastic modulus in the range of 30 MPa to 3000 MPa. In the case of a bump 5 composed of a lead-free solder, the underfill 6 is composed of a resin material having an elastic modulus in the range of 150 MPa to 800 MPa. An insulating layer 311 of buildup layers 31 of the substrate 3 has a linear expansion coefficient of 35 ppm/° C. or less in the in-plane direction of the substrate at temperatures in the range of 25° C. to the glass transition temperature.Type: GrantFiled: April 20, 2007Date of Patent: January 14, 2014Assignee: Sumitomo Bakelite Co., Ltd.Inventors: Mitsuo Sugino, Takeshi Hosomi, Masahiro Wada, Masataka Arai
-
Patent number: 8598719Abstract: A semiconductor element mounting board includes: a board having surfaces; a semiconductor element provided at a side of one of the surfaces of the board; a bonding agent layer through which the board and the semiconductor element are bonded together, the bonding agent layer having a storage modulus at 25° C. of 5 to 1,000 MPa; a first layer into which the semiconductor element is embedded, the first layer provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer.Type: GrantFiled: June 3, 2009Date of Patent: December 3, 2013Assignee: Sumitomo Bakelite Company LimitedInventors: Mitsuo Sugino, Hideki Hara, Toru Meura
-
Patent number: 8269332Abstract: A semiconductor element mounting board includes: aboard having surfaces; a semiconductor element mounted on one of the surfaces of the board; a first layer into which the semiconductor element is embedded, the first layer being provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer. In such a semiconductor element mounting board, each of the surface layers has rigidity higher than that of each of the first and second layers. It is preferred that in the case where a Young's modulus of each surface layer at 25° C. is defined as X GPa and a Young's modulus of the first layer at 25° C.Type: GrantFiled: October 15, 2008Date of Patent: September 18, 2012Assignee: Sumitomo Bakelite Company, Ltd.Inventors: Mitsuo Sugino, Hideki Hara, Toru Meura
-
Patent number: 8268540Abstract: A method of manufacturing a light receiving device 1 includes: providing a resin layer 14 containing a photo curing resin on a transparent substrate 13 where a plurality of transparent substrate portions 13A are integrated so that the resin layer covers the transparent substrate 13; selectively irradiating the resin layer 14 with light, followed by a developing process, so that the resin layer 14 remains in regions of the transparent substrate 13 which surround portions corresponding to regions facing light receiving portions 11 in the transparent substrate portions 13A; dividing the transparent substrate 13 into units of transparent substrate portions 13A so that a plurality of transparent substrate portions 13A are obtained; dividing the base substrate 12 into units of base substrate portions 12A so that a plurality of base substrate portions 12A are obtained; and joining the base substrate portions 12A and the transparent substrate portions 13A via the resin layer 14.Type: GrantFiled: May 30, 2007Date of Patent: September 18, 2012Assignee: Sumitomo Bakelite Company, Ltd.Inventors: Toyosei Takahashi, Junya Kusunoki, Kazuto Oonami, Mitsuo Sugino, Masakazu Kawata, Rie Takayama, Seiji Oohashi
-
Patent number: 8247270Abstract: A method of manufacturing a semiconductor component of the present invention has: obtaining a semiconductor wafer having stud electrodes formed on a functional surface thereof, and a circuit board having solder bumps on one surface and having electrode pads on the other surface thereof; bonding the semiconductor wafer and the circuit board, while providing a resin layer having a flux activity between the semiconductor wafer and the circuit board, and so as to bring the stud electrodes into contact with the solder bumps, while penetrating the resin layer having a flux activity, to thereby obtain a bonded structure; applying a solder material onto the electrode pads of the bonded structure; and dicing the bonded structure to obtain a plurality of semiconductor components.Type: GrantFiled: May 13, 2009Date of Patent: August 21, 2012Assignee: Sumitomo Bakelite Co., Ltd.Inventors: Hiroki Nikaido, Mitsuo Sugino
-
Patent number: 8039305Abstract: In a method for bonding semiconductor wafers of the present invention, a bonding layer containing a flux-active curing agent and a thermosetting resin is interposed between a first semiconductor wafer and a second semiconductor wafer, thereby producing a semiconductor wafer stacked body in which the first and second semiconductor wafers are stacked together, and then the semiconductor wafer stacked body is compressed in a thickness direction thereof while heating it so that the first and second semiconductor wafers are fixed together by melting and solidifying solder bumps while curing the thermosetting resin, thereby producing a semiconductor wafer bonded body in which first connector portions and second connector portions are electrically connected together through solidified products obtained by melting and solidifying the solder bumps.Type: GrantFiled: April 24, 2008Date of Patent: October 18, 2011Assignee: Sumitomo Bakelite Company, Ltd.Inventors: Kenzou Mejima, Satoru Katsurayama, Mitsuo Sugino
-
Patent number: 8034651Abstract: A light receiving device 1 includes a support substrate 12 provided thereon with a photodetector 11 including a photodetecting portion 111 and a base substrate 112 on which the photodetecting portion 111 is placed; and a transparent substrate 13 disposed so as to oppose the face of the support substrate 12 on which the photodetector 11 is provided. Between the support substrate 12 and the transparent substrate 13, a frame portion 14 is provided so as to surround the photodetector 11. The frame portion 14 is a photo-curing adhesive, and directly adhered to the transparent substrate 13 and the support substrate 12. Such structure provides a light receiving device capable of exhibiting the desired performance, and a method of manufacturing such light receiving device can also be provided.Type: GrantFiled: February 19, 2008Date of Patent: October 11, 2011Assignee: Sumitomo Bakelite Co., Ltd.Inventors: Toyosei Takahashi, Rie Takayama, Mitsuo Sugino, Masakazu Kawata
-
Publication number: 20110084409Abstract: A semiconductor element mounting board includes: a board having surfaces; a semiconductor element provided at a side of one of the surfaces of the board; a bonding agent layer through which the board and the semiconductor element are bonded together, the bonding agent layer having a storage modulus at 25° C. of 5 to 1,000 MPa; a first layer into which the semiconductor element is embedded, the first layer provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer.Type: ApplicationFiled: June 3, 2009Publication date: April 14, 2011Inventors: Mitsuo Sugino, Hideki Hara, Toru Meura
-
Publication number: 20110037174Abstract: A method of manufacturing a semiconductor component of the present invention has: obtaining a semiconductor wafer having stud electrodes formed on a functional surface thereof, and a circuit board having solder bumps on one surface and having electrode pads on the other surface thereof; bonding the semiconductor wafer and the circuit board, while providing a resin layer having a flux activity between the semiconductor wafer and the circuit board, and so as to bring the stud electrodes into contact with the solder bumps, while penetrating the resin layer having a flux activity, to thereby obtain a bonded structure; applying a solder material onto the electrode pads of the bonded structure; and dicing the bonded structure to obtain a plurality of semiconductor components.Type: ApplicationFiled: May 13, 2009Publication date: February 17, 2011Applicant: SUMITOMO BAKELITE CO., LTD.Inventors: Hiroki Nikaido, Mitsuo Sugino
-
Patent number: 7829992Abstract: A semiconductor device (100) comprises a first resin substrate (101) on which a first semiconductor chip (125) is mounted a surface thereof; a second resin substrate (111) on which a second semiconductor chip (131) is mounted on a surface thereof; and a resin base material (109), joined to a front surface of the first resin substrate (101) and to a back surface of the second resin substrate (111), so that these surfaces are electrically connected. The resin base material (109) is disposed in a circumference of the first resin substrate (101) in the surface of the first resin substrate (101). Further, the first semiconductor chip (125) is disposed in a space section provided among the first resin substrate (101), the second resin substrate (111) and the resin base material (109) in the surface of the first resin substrate (101).Type: GrantFiled: April 24, 2007Date of Patent: November 9, 2010Assignee: Sumitomo Bakelite Company, Ltd.Inventors: Mitsuo Sugino, Satoru Katsurayama, Tomoe Yamashiro, Tetsuya Miyamoto, Hiroyuki Yamashita
-
Publication number: 20100258713Abstract: A light receiving device 1 includes a support substrate 12 provided thereon with a photodetector 11 including a photodetecting portion 111 and a base substrate 112 on which the photodetecting portion 111 is placed; and a transparent substrate 13 disposed so as to oppose the face of the support substrate 12 on which the photodetector 11 is provided. Between the support substrate 12 and the transparent substrate 13, a frame portion 14 is provided so as to surround the photodetector 11. The frame portion 14 is a photo-curing adhesive, and directly adhered to the transparent substrate 13 and the support substrate 12. Such structure provides a light receiving device capable of exhibiting the desired performance, and a method of manufacturing such light receiving device can also be provided.Type: ApplicationFiled: February 19, 2008Publication date: October 14, 2010Applicant: Sumitomo Bakelite Co., LtdInventors: Toyosei Takahashi, Rie Takayama, Mitsuo Sugino, Masakazu Kawata
-
Publication number: 20100213597Abstract: A semiconductor element mounting board includes: aboard having surfaces; a semiconductor element mounted on one of the surfaces of the board; a first layer into which the semiconductor element is embedded, the first layer being provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer. In such a semiconductor element mounting board, each of the surface layers has rigidity higher than that of each of the first and second layers. It is preferred that in the case where a Young's modulus of each surface layer at 25° C. is defined as X GPa and a Young's modulus of the first layer at 25° C.Type: ApplicationFiled: October 15, 2008Publication date: August 26, 2010Applicant: SUMITOMO BAKELITE COMPANY LIMITEDInventors: Mitsuo Sugino, Hideki Hara, Toru Meura
-
Publication number: 20100186938Abstract: A heat transfer sheet of the present invention includes a heat transfer layer having a first portion and a second portion provided in a position different from the first portion in a planar view of the heat transfer layer, the second portion being capable of expanding and contracting in a thickness direction of the heat transfer layer at an expansion ratio larger than that of the first portion depending on temperature changes in an object from which heat is to be dissipated.Type: ApplicationFiled: January 28, 2008Publication date: July 29, 2010Applicant: Sumitomo Bakelite Company LimitedInventors: Takashi Murata, Yoshiyuki Nakamura, Izumi Takahashi, Hatsuhiro Soh, Kazumoto Shimizu, Yoshihide Nii, Shinichiro Ito, Hitoshi Kawaguchi, Mitsuo Sugino
-
Publication number: 20100181686Abstract: A semiconductor device 1 is equipped with a first substrate 3 on which a first semiconductor chip 2 is mounted, a second substrate 5 on which a second semiconductor chip 4 is mounted, and connecting sections 6 that electrically connect the first substrate 3 and the second substrate 5. The first substrate 3 has build-up layers 31A and 31B in each of which an insulating layer 311 containing a resin and conductor interconnect layers 312 and 313 are laminated alternately, and the respective conductor interconnect layers 312 are connected by a conductive layer 314 provided in via holes of the insulating layers 311. The second substrate 5 also has build-up layers 31A and 31B.Type: ApplicationFiled: May 15, 2007Publication date: July 22, 2010Inventors: Mitsuo Sugino, Satoru Katsurayama, Hiroyuki Yamashita
-
Patent number: 7759794Abstract: A semiconductor device 100 has a BGA substrate 110, a semiconductor chip 101, a bump 106 and an underfill 108 filling the periphery of the bump. An interlayer dielectric 104 in the semiconductor chip 101 contains a low dielectric constant film. The bump 106 is comprised of a lead-free solder. The underfill 108 is comprised of a resin material having an elastic modulus of 150 MPa to 800 MPa both inclusive, and a linear expansion coefficient of the BGA substrate 110 in an in-plane direction of the substrate is less than 14 ppm/° C.Type: GrantFiled: March 9, 2006Date of Patent: July 20, 2010Assignee: Sumitomo Bakelite Company, Ltd.Inventors: Mitsuo Sugino, Takeshi Hosomi, Yushi Sakamoto
-
Publication number: 20100129960Abstract: In a method for bonding semiconductor wafers of the present invention, a bonding layer containing a flux-active curing agent and a thermosetting resin is interposed between a first semiconductor wafer and a second semiconductor wafer, thereby producing a semiconductor wafer stacked body in which the first and second semiconductor wafers are stacked together, and then the semiconductor wafer stacked body is compressed in a thickness direction thereof while heating it so that the first and second semiconductor wafers are fixed together by melting and solidifying solder bumps while curing the thermosetting resin, thereby producing a semiconductor wafer bonded body in which first connector portions and second connector portions are electrically connected together through solidified products obtained by melting and solidifying the solder bumps.Type: ApplicationFiled: April 24, 2008Publication date: May 27, 2010Applicant: Sumitomo Bakelite Company LimitedInventors: Kenzou Mejima, Satoru Katsurayama, Mitsuo Sugino
-
Publication number: 20090321919Abstract: The semiconductor device 1 includes a substrate 3, a semiconductor chip 4 mounted on the substrate 3, the substrate 3, a bump 5 connecting the substrate 3 and the semiconductor chip 4, and an underfill 6 filling in around the bump 5. In the case of a bump 5 composed of a high-melting-point solder having a melting point of 230° C. or more, the underfill 6 is composed of a resin material having an elastic modulus in the range of 30 MPa to 3000 MPa. In the case of a bump 5 composed of a lead-free solder, the underfill 6 is composed of a resin material having an elastic modulus in the range of 150 MPa to 800 MPa. An insulating layer 311 of buildup layers 31 of the substrate 3 has a linear expansion coefficient of 35 ppm/° C. or less in the in-plane direction of the substrate at temperatures in the range of 25° C. to the glass transition temperature.Type: ApplicationFiled: April 20, 2007Publication date: December 31, 2009Inventors: Mitsuo Sugino, Takeshi Hosomi, Masahiro Wada, Masataka Arai
-
Publication number: 20090243065Abstract: A semiconductor device (100) comprises a first resin substrate (101) on which a first semiconductor chip (125) is mounted a surface thereof; a second resin substrate (111) on which a second semiconductor chip (131) is mounted on a surface thereof; and a resin base material (109), joined to a front surface of the first resin substrate (101) and to a back surface of the second resin substrate (111), so that these surfaces are electrically connected. The resin base material (109) is disposed in a circumference of the first resin substrate (101) in the surface of the first resin substrate (101). Further, the first semiconductor chip (125) is disposed in a space section provided among the first resin substrate (101), the second resin substrate (111) and the resin base material (109) in the surface of the first resin substrate (101).Type: ApplicationFiled: April 24, 2007Publication date: October 1, 2009Inventors: Mitsuo Sugino, Satoru Katsurayama, Tomoe Yamashiro, Tetsuya Miyamoto, Hiroyuki Yamashita