Patents by Inventor Mitsuo Teramoto

Mitsuo Teramoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Test pattern generation for logic circuits with reduced backtracking operations
    Patent number: 5602856
    Abstract: A scheme for generating test patterns for logic circuits which can generate the test patterns effectively and efficiently by making the assignments of the fewer logic values at earlier stages, so as to reduce the number of backtracking operations required.
    Type: Grant
    Filed: April 5, 1994
    Date of Patent: February 11, 1997
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventor: Mitsuo Teramoto