Abstract: A memory device coupled to a data flow processor inserted in token ring. Its operation is initiated upon receiving incoming tokens including an instruction code and information. The instruction code includes a memory read instruction, a memory write instruction, an extended address set instruction, and a write data set instruction. The memory device comprises a memory unit, a first register for holding a data, a second register for holding an extended address, and control circuitry operative to control each operation of the memory unit and the registers.