Patents by Inventor Mitsuru ANAZAWA

Mitsuru ANAZAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11073896
    Abstract: A storage device comprises a nonvolatile memory, a controller that controls access to the nonvolatile memory, and a power circuit that supplies power to the nonvolatile memory and the controller. The power circuit can control the supply of power to at least parts of the nonvolatile memory and at least parts of the controller. The controller executes a data save process when a sleep transition request is received from the host requesting at least one of a plurality of sleep states according to a requested sleep state of the sleep transition request. The controller provides the host with state transition determination information that includes at one of a power consumption amount for a transition to a sleep state from an idle state and power consumption amount for a transition from the sleep state to the idle state.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mitsuru Anazawa, Norikazu Yoshida, Takashi Yamaguchi
  • Patent number: 11042304
    Abstract: A memory system includes first and second non-volatile memories and a memory controller respectively connected to the first and second non-volatile memories via first and second channels. The memory controller executes a first read operation of reading first data from the first non-volatile memory and a second read operation of reading second data from the second non-volatile memory in parallel in response to a first read request received from the outside, and sets a first transfer rate of the first channel to be lower than a second transfer rate of the second channel when a first time at which the first read operation is scheduled to be completed is earlier than a second time at which the second read operation is scheduled to be completed.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: June 22, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Mitsuru Anazawa
  • Publication number: 20200293198
    Abstract: A memory system includes first and second non-volatile memories and a memory controller respectively connected to the first and second non-volatile memories via first and second channels. The memory controller executes a first read operation of reading first data from the first non-volatile memory and a second read operation of reading second data from the second non-volatile memory in parallel in response to a first read request received from the outside, and sets a first transfer rate of the first channel to be lower than a second transfer rate of the second channel when a first time at which the first read operation is scheduled to be completed is earlier than a second time at which the second read operation is scheduled to be completed.
    Type: Application
    Filed: August 8, 2019
    Publication date: September 17, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Mitsuru ANAZAWA
  • Patent number: 10599208
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller executes access to the nonvolatile memory based on a command from a host device. The controller includes a processor, a data memory and a monitoring circuit. The monitoring circuit monitors writing to the data memory by a certain processing circuit in the controller and transmits a first notification to the processor when receiving the writing.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: March 24, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyasu Nakatsuka, Mitsunori Tadokoro, Mitsuru Anazawa
  • Patent number: 10445018
    Abstract: A switch according to an embodiment includes a first PCIe interface that can be connected to a host on the basis of a PCIe standard. In addition, the switch includes a plurality of second PCIe interfaces that can be connected to a plurality of storage devices, respectively, on the basis of the PCIe standard. The switch further includes a control unit that distributes an access request which is comply with an NVMe standard and is transmitted from the host to any one of the plurality of second PCIe interfaces. The distribution includes a process of constructing an NVMe command of the access request and a process of constructing a data transmission descriptor list of the access request.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: October 15, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Yamaguchi, Norikazu Yoshida, Mitsuru Anazawa
  • Publication number: 20190286219
    Abstract: A storage device comprises a nonvolatile memory, a controller that controls access to the nonvolatile memory, and a power circuit that supplies power to the nonvolatile memory and the controller. The power circuit can control the supply of power to at least parts of the nonvolatile memory and at least parts of the controller. The controller executes a data save process when a sleep transition request is received from the host requesting at least one of a plurality of sleep states according to a requested sleep state of the sleep transition request. The controller provides the host with state transition determination information that includes at one of a power consumption amount for a transition to a sleep state from an idle state and power consumption amount for a transition from the sleep state to the idle state.
    Type: Application
    Filed: October 30, 2018
    Publication date: September 19, 2019
    Inventors: Mitsuru ANAZAWA, Norikazu YOSHIDA, Takashi YAMAGUCHI
  • Patent number: 10061527
    Abstract: A memory system includes non-volatile memory. The memory system includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host. The power supply unit adjusts the voltage supplied to the module in accordance with a command from the power supply control unit.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: August 28, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoon Tze Chin, Norikazu Yoshida, Mitsuru Anazawa
  • Publication number: 20180074757
    Abstract: A switch according to an embodiment includes a first PCIe interface that can be connected to a host on the basis of a PCIe standard. In addition, the switch includes a plurality of second PCIe interfaces that can be connected to a plurality of storage devices, respectively, on the basis of the PCIe standard. The switch further includes a control unit that distributes an access request which is comply with an NVMe standard and is transmitted from the host to any one of the plurality of second PCIe interfaces. The distribution includes a process of constructing an NVMe command of the access request and a process of constructing a data transmission descriptor list of the access request.
    Type: Application
    Filed: March 6, 2017
    Publication date: March 15, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi YAMAGUCHI, Norikazu YOSHIDA, Mitsuru ANAZAWA
  • Publication number: 20180018119
    Abstract: A memory system according to an embodiment includes non-volatile memory. The memory system includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 18, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Yoon Tze CHIN, Norikazu YOSHIDA, Mitsuru ANAZAWA
  • Patent number: 9804795
    Abstract: A memory including non-volatile memory. The memory system also includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host. The power supply unit adjusts the voltage supplied to the module in accordance with a command from the power supply control unit.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 31, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoon Tze Chin, Norikazu Yoshida, Mitsuru Anazawa
  • Publication number: 20170068479
    Abstract: A memory system according to an embodiment includes non-volatile memory. The memory system includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host.
    Type: Application
    Filed: March 4, 2016
    Publication date: March 9, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoon Tze CHIN, Norikazu Yoshida, Mitsuru Anazawa
  • Publication number: 20170068478
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller executes access to the nonvolatile memory based on a command from a host device. The controller includes a processor, a data memory and a monitoring circuit. The monitoring circuit monitors writing to the data memory by a certain processing circuit in the controller and transmits a first notification to the processor when receiving the writing.
    Type: Application
    Filed: March 4, 2016
    Publication date: March 9, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyasu NAKATSUKA, Mitsunori TADOKORO, Mitsuru ANAZAWA
  • Patent number: 9568987
    Abstract: According to one embodiment, a memory system includes a volatile memory, a nonvolatile memory, and a controller which is configured to turn off a power of the volatile memory after storing data of the volatile memory in the nonvolatile memory in a first mode, turn on the power of the volatile memory in the second mode, and change a first timing as a future timing switching to the first mode based on a second timing as a past timing switching to the second mode.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: February 14, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuru Anazawa, Toshikatsu Hida, Shohei Asami
  • Publication number: 20160266638
    Abstract: According to one embodiment, a memory system includes a volatile memory, a nonvolatile memory, and a controller which is configured to turn off a power of the volatile memory after storing data of the volatile memory in the nonvolatile memory in a first mode, turn on the power of the volatile memory in the second mode, and change a first timing as a future timing switching to the first mode based on a second timing as a past timing switching to the second mode.
    Type: Application
    Filed: July 10, 2015
    Publication date: September 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mitsuru ANAZAWA, Toshikatsu HIDA, Shohei ASAMI