Patents by Inventor Mitsuru ANAZAWA
Mitsuru ANAZAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11073896Abstract: A storage device comprises a nonvolatile memory, a controller that controls access to the nonvolatile memory, and a power circuit that supplies power to the nonvolatile memory and the controller. The power circuit can control the supply of power to at least parts of the nonvolatile memory and at least parts of the controller. The controller executes a data save process when a sleep transition request is received from the host requesting at least one of a plurality of sleep states according to a requested sleep state of the sleep transition request. The controller provides the host with state transition determination information that includes at one of a power consumption amount for a transition to a sleep state from an idle state and power consumption amount for a transition from the sleep state to the idle state.Type: GrantFiled: October 30, 2018Date of Patent: July 27, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Mitsuru Anazawa, Norikazu Yoshida, Takashi Yamaguchi
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Patent number: 11042304Abstract: A memory system includes first and second non-volatile memories and a memory controller respectively connected to the first and second non-volatile memories via first and second channels. The memory controller executes a first read operation of reading first data from the first non-volatile memory and a second read operation of reading second data from the second non-volatile memory in parallel in response to a first read request received from the outside, and sets a first transfer rate of the first channel to be lower than a second transfer rate of the second channel when a first time at which the first read operation is scheduled to be completed is earlier than a second time at which the second read operation is scheduled to be completed.Type: GrantFiled: August 8, 2019Date of Patent: June 22, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventor: Mitsuru Anazawa
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Publication number: 20200293198Abstract: A memory system includes first and second non-volatile memories and a memory controller respectively connected to the first and second non-volatile memories via first and second channels. The memory controller executes a first read operation of reading first data from the first non-volatile memory and a second read operation of reading second data from the second non-volatile memory in parallel in response to a first read request received from the outside, and sets a first transfer rate of the first channel to be lower than a second transfer rate of the second channel when a first time at which the first read operation is scheduled to be completed is earlier than a second time at which the second read operation is scheduled to be completed.Type: ApplicationFiled: August 8, 2019Publication date: September 17, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Mitsuru ANAZAWA
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Patent number: 10599208Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller executes access to the nonvolatile memory based on a command from a host device. The controller includes a processor, a data memory and a monitoring circuit. The monitoring circuit monitors writing to the data memory by a certain processing circuit in the controller and transmits a first notification to the processor when receiving the writing.Type: GrantFiled: March 4, 2016Date of Patent: March 24, 2020Assignee: Toshiba Memory CorporationInventors: Hiroyasu Nakatsuka, Mitsunori Tadokoro, Mitsuru Anazawa
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Patent number: 10445018Abstract: A switch according to an embodiment includes a first PCIe interface that can be connected to a host on the basis of a PCIe standard. In addition, the switch includes a plurality of second PCIe interfaces that can be connected to a plurality of storage devices, respectively, on the basis of the PCIe standard. The switch further includes a control unit that distributes an access request which is comply with an NVMe standard and is transmitted from the host to any one of the plurality of second PCIe interfaces. The distribution includes a process of constructing an NVMe command of the access request and a process of constructing a data transmission descriptor list of the access request.Type: GrantFiled: March 6, 2017Date of Patent: October 15, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takashi Yamaguchi, Norikazu Yoshida, Mitsuru Anazawa
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Publication number: 20190286219Abstract: A storage device comprises a nonvolatile memory, a controller that controls access to the nonvolatile memory, and a power circuit that supplies power to the nonvolatile memory and the controller. The power circuit can control the supply of power to at least parts of the nonvolatile memory and at least parts of the controller. The controller executes a data save process when a sleep transition request is received from the host requesting at least one of a plurality of sleep states according to a requested sleep state of the sleep transition request. The controller provides the host with state transition determination information that includes at one of a power consumption amount for a transition to a sleep state from an idle state and power consumption amount for a transition from the sleep state to the idle state.Type: ApplicationFiled: October 30, 2018Publication date: September 19, 2019Inventors: Mitsuru ANAZAWA, Norikazu YOSHIDA, Takashi YAMAGUCHI
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Patent number: 10061527Abstract: A memory system includes non-volatile memory. The memory system includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host. The power supply unit adjusts the voltage supplied to the module in accordance with a command from the power supply control unit.Type: GrantFiled: September 25, 2017Date of Patent: August 28, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yoon Tze Chin, Norikazu Yoshida, Mitsuru Anazawa
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Publication number: 20180074757Abstract: A switch according to an embodiment includes a first PCIe interface that can be connected to a host on the basis of a PCIe standard. In addition, the switch includes a plurality of second PCIe interfaces that can be connected to a plurality of storage devices, respectively, on the basis of the PCIe standard. The switch further includes a control unit that distributes an access request which is comply with an NVMe standard and is transmitted from the host to any one of the plurality of second PCIe interfaces. The distribution includes a process of constructing an NVMe command of the access request and a process of constructing a data transmission descriptor list of the access request.Type: ApplicationFiled: March 6, 2017Publication date: March 15, 2018Applicant: TOSHIBA MEMORY CORPORATIONInventors: Takashi YAMAGUCHI, Norikazu YOSHIDA, Mitsuru ANAZAWA
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Publication number: 20180018119Abstract: A memory system according to an embodiment includes non-volatile memory. The memory system includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host.Type: ApplicationFiled: September 25, 2017Publication date: January 18, 2018Applicant: Toshiba Memory CorporationInventors: Yoon Tze CHIN, Norikazu YOSHIDA, Mitsuru ANAZAWA
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Patent number: 9804795Abstract: A memory including non-volatile memory. The memory system also includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host. The power supply unit adjusts the voltage supplied to the module in accordance with a command from the power supply control unit.Type: GrantFiled: March 4, 2016Date of Patent: October 31, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yoon Tze Chin, Norikazu Yoshida, Mitsuru Anazawa
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Publication number: 20170068479Abstract: A memory system according to an embodiment includes non-volatile memory. The memory system includes a controller that controls data transfer between a host and the non-volatile memory, and a power supply unit that supplies a voltage to the controller. Further, the controller includes a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation condition determined with the host.Type: ApplicationFiled: March 4, 2016Publication date: March 9, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Yoon Tze CHIN, Norikazu Yoshida, Mitsuru Anazawa
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Publication number: 20170068478Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller executes access to the nonvolatile memory based on a command from a host device. The controller includes a processor, a data memory and a monitoring circuit. The monitoring circuit monitors writing to the data memory by a certain processing circuit in the controller and transmits a first notification to the processor when receiving the writing.Type: ApplicationFiled: March 4, 2016Publication date: March 9, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyasu NAKATSUKA, Mitsunori TADOKORO, Mitsuru ANAZAWA
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Patent number: 9568987Abstract: According to one embodiment, a memory system includes a volatile memory, a nonvolatile memory, and a controller which is configured to turn off a power of the volatile memory after storing data of the volatile memory in the nonvolatile memory in a first mode, turn on the power of the volatile memory in the second mode, and change a first timing as a future timing switching to the first mode based on a second timing as a past timing switching to the second mode.Type: GrantFiled: July 10, 2015Date of Patent: February 14, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuru Anazawa, Toshikatsu Hida, Shohei Asami
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Publication number: 20160266638Abstract: According to one embodiment, a memory system includes a volatile memory, a nonvolatile memory, and a controller which is configured to turn off a power of the volatile memory after storing data of the volatile memory in the nonvolatile memory in a first mode, turn on the power of the volatile memory in the second mode, and change a first timing as a future timing switching to the first mode based on a second timing as a past timing switching to the second mode.Type: ApplicationFiled: July 10, 2015Publication date: September 15, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuru ANAZAWA, Toshikatsu HIDA, Shohei ASAMI
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Patent number: RE49273Abstract: A switch according to an embodiment includes a first PCIe interface that can be connected to a host on the basis of a PCIe standard. In addition, the switch includes a plurality of second PCIe interfaces that can be connected to a plurality of storage devices, respectively, on the basis of the PCIe standard. The switch further includes a control unit that distributes an access request which is comply with an NVMe standard and is transmitted from the host to any one of the plurality of second PCIe interfaces. The distribution includes a process of constructing an NVMe command of the access request and a process of constructing a data transmission descriptor list of the access request.Type: GrantFiled: September 4, 2020Date of Patent: November 1, 2022Assignee: KIOXIA CORPORATIONInventors: Takashi Yamaguchi, Norikazu Yoshida, Mitsuru Anazawa