Patents by Inventor Mitsuru Ekawa
Mitsuru Ekawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966104Abstract: An optical modulator includes a substrate having a main surface including a first area and a second area, an optical modulation portion disposed on the first area, and an optical waveguide portion disposed on the second area. The optical modulation portion includes a first mesa waveguide and an electrode connected to the first mesa waveguide. The first mesa waveguide includes a p-type semiconductor layer, a first core layer, and an n-type semiconductor layer. The optical waveguide portion includes a second mesa waveguide. The second mesa waveguide includes a first cladding layer, a second core layer, and a second cladding layer. The second core layer is optically coupled to the first core layer. The first cladding layer contains a p-type dopant and protons. The second cladding layer contains an n-type dopant.Type: GrantFiled: May 19, 2022Date of Patent: April 23, 2024Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Makoto Ogasawara, Naoya Kono, Mitsuru Ekawa
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Publication number: 20220397802Abstract: An optical modulator includes a first mesa waveguide extending in a first direction, and a second mesa waveguide. The first mesa waveguide includes a p-type first semiconductor layer disposed over a substrate, a core layer disposed over the first semiconductor layer, a p-type second semiconductor layer disposed over the core layer, and an n-type third semiconductor layer disposed over the core layer. The second semiconductor layer and the third semiconductor layer are arranged adjacent to each other in the first direction. An electrode is disposed over the third semiconductor layer. A joining surface between the second semiconductor layer and the third semiconductor layer is inclined with respect to a surface orthogonal to the first direction.Type: ApplicationFiled: June 7, 2022Publication date: December 15, 2022Applicant: Sumitomo Electric Industries, Ltd.Inventors: Hiroki MORI, Naoya KONO, Mitsuru EKAWA
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Publication number: 20220390774Abstract: An optical modulator includes a substrate having a main surface including a first area and a second area, an optical modulation portion disposed on the first area, and an optical waveguide portion disposed on the second area. The optical modulation portion includes a first mesa waveguide and an electrode connected to the first mesa waveguide. The first mesa waveguide includes a p-type semiconductor layer, a first core layer, and an n-type semiconductor layer. The optical waveguide portion includes a second mesa waveguide. The second mesa waveguide includes a first cladding layer, a second core layer, and a second cladding layer. The second core layer is optically coupled to the first core layer. The first cladding layer contains a p-type dopant and protons. The second cladding layer contains an n-type dopant.Type: ApplicationFiled: May 19, 2022Publication date: December 8, 2022Applicant: Sumitomo Electric Industries, Ltd.Inventors: Makoto OGASAWARA, Naoya KONO, Mitsuru EKAWA
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Publication number: 20220199866Abstract: A semiconductor optical device, in which a light emitting region and a modulator region are integrated, includes a first mesa disposed in the light emitting region, protruding in a direction that intersects a light propagation direction, and including an active layer, first and second buried layers disposed on the first mesa in a direction that intersects the light propagation direction and sequentially stacked in a direction in which the first mesa protrudes, a first semiconductor layer disposed on the first mesa and the second buried layer, a second mesa disposed in the modulator region and including a light absorption layer, and a third buried layer disposed on the second mesa. The first semiconductor layer and the first buried layer each have a first conductivity type. The second buried layer has a second conductivity type different from the first conductivity type, and the third buried layer is a semi-insulating semiconductor layer.Type: ApplicationFiled: November 18, 2021Publication date: June 23, 2022Applicant: Sumitomo Electric Industries, Ltd.Inventors: Yuki ITO, Mitsuru EKAWA
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Patent number: 8987117Abstract: A semiconductor optical integrated device includes a first semiconductor optical device formed over a (001) plane of a substrate and a second semiconductor optical device which is formed over the (001) plane of the substrate in a (110) orientation from the first semiconductor optical device and which is optically connected to the first semiconductor optical device. The first semiconductor optical device includes a first core layer and a first clad layer which is formed over the first core layer and which has a crystal surface on a side on a second semiconductor optical device side that forms an angle ? greater than or equal to 55 degrees and less than or equal to 90 degrees with the (001) plane.Type: GrantFiled: August 14, 2013Date of Patent: March 24, 2015Assignee: Fujitsu LimitedInventors: Shigekazu Okumura, Mitsuru Ekawa, Shuichi Tomabechi, Ayahito Uetake
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Publication number: 20130330867Abstract: A semiconductor optical integrated device includes a first semiconductor optical device formed over a (001) plane of a substrate and a second semiconductor optical device which is formed over the (001) plane of the substrate in a (110) orientation from the first semiconductor optical device and which is optically connected to the first semiconductor optical device. The first semiconductor optical device includes a first core layer and a first clad layer which is formed over the first core layer and which has a crystal surface on a side on a second semiconductor optical device side that forms an angle ? greater than or equal to 55 degrees and less than or equal to 90 degrees with the (001) plane.Type: ApplicationFiled: August 14, 2013Publication date: December 12, 2013Applicant: FUJITSU LIMITEDInventors: Shigekazu OKUMURA, Mitsuru EKAWA, Shuichi TOMABECHI, Ayahito UETAKE
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Patent number: 8565279Abstract: A semiconductor optical integrated device includes a first semiconductor optical device formed over a (001) plane of a substrate and a second semiconductor optical device which is formed over the (001) plane of the substrate in a (110) orientation from the first semiconductor optical device and which is optically connected to the first semiconductor optical device. The first semiconductor optical device includes a first core layer and a first clad layer which is formed over the first core layer and which has a crystal surface on a side on a second semiconductor optical device side that forms an angle ? greater than or equal to 55 degrees and less than or equal to 90 degrees with the (001) plane.Type: GrantFiled: September 12, 2012Date of Patent: October 22, 2013Assignee: Fujitsu LimitedInventors: Shigekazu Okumura, Mitsuru Ekawa, Shuichi Tomabechi, Ayahito Uetake
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Publication number: 20130010824Abstract: A semiconductor optical integrated device includes a first semiconductor optical device formed over a (001) plane of a substrate and a second semiconductor optical device which is formed over the (001) plane of the substrate in a (110) orientation from the first semiconductor optical device and which is optically connected to the first semiconductor optical device. The first semiconductor optical device includes a first core layer and a first clad layer which is formed over the first core layer and which has a crystal surface on a side on a second semiconductor optical device side that forms an angle ? greater than or equal to 55 degrees and less than or equal to 90 degrees with the (001) plane.Type: ApplicationFiled: September 12, 2012Publication date: January 10, 2013Applicant: FUJITSU LIMITEDInventors: Shigekazu OKUMURA, Mitsuru Ekawa, Shuichi Tomabechi, Ayahito Uetake
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Patent number: 7924896Abstract: An optical semiconductor device includes an active layer, a first semiconductor layer formed above the active layer and made from a semiconductor material containing Al, a second semiconductor layer formed above the first semiconductor layer and made from a semiconductor material which does not contain any one of Al and P and whose band gap is greater than that of the active layer, and a third semiconductor layer formed above the second semiconductor layer and made from a semiconductor material which does not contain Al but contains P. The second semiconductor layer is formed such that the first semiconductor layer and the third semiconductor layer do not contact with each other.Type: GrantFiled: September 19, 2008Date of Patent: April 12, 2011Assignee: Fujitsu LimitedInventors: Tsuyoshi Yamamoto, Manabu Matsuda, Mitsuru Ekawa, Kan Takada, Shigekazu Okumura
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Patent number: 7804870Abstract: In a p-type clad layer, not only a p-type dopant Zn but also Fe is doped. Its Zn concentration is 1.5×1018 cm?3 and the Fe concentration is 1.8×1017 cm?3. In a semi-insulating burying layer, Fe is doped as an impurity generating a deep acceptor level and the concentration thereof is 6.0×1016 cm?3. The Fe concentration in the p-type clad layer is thus three times higher than the Fe concentration in the burying layer.Type: GrantFiled: March 21, 2008Date of Patent: September 28, 2010Assignees: Fujitsu Limited, Sumitomo Electric Device Innovations, Inc.Inventors: Kan Takada, Mitsuru Ekawa, Tsuyoshi Yamamoto, Tatsuya Takeuchi
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Publication number: 20090052487Abstract: An optical semiconductor device includes an active layer, a first semiconductor layer formed above the active layer and made from a semiconductor material containing Al, a second semiconductor layer formed above the first semiconductor layer and made from a semiconductor material which does not contain any one of Al and P and whose band gap is greater than that of the active layer, and a third semiconductor layer formed above the second semiconductor layer and made from a semiconductor material which does not contain Al but contains P. The second semiconductor layer is formed such that the first semiconductor layer and the third semiconductor layer do not contact with each other.Type: ApplicationFiled: September 19, 2008Publication date: February 26, 2009Applicant: FUJITSU LIMITEDInventors: Tsuyoshi Yamamoto, Manabu Matsuda, Mitsuru Ekawa, Kan Takada, Shigekazu Okumura
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Patent number: 7482617Abstract: In order to prevent As/P replacement at the boundary face of a re-grown semiconductor layer and avoid a crystalline defect caused by the replacement, there is provided an optical semiconductor device comprising: a semiconductor substrate; a striped stacking body including a first semiconductor layer, an active layer, and a second semiconductor layer; and a burying layer burying the striped stacking body striped stacking body, wherein surfaces in contact with a side face and a bottom face of the burying layer are made of a compound semiconductor that contains arsenic (As) alone as a group V element, and a portion other than the surface includes a group V element other than arsenic.Type: GrantFiled: October 6, 2005Date of Patent: January 27, 2009Assignee: Fujitsu LimitedInventors: Tsuyoshi Yamamoto, Mitsuru Ekawa
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Publication number: 20080240191Abstract: In a p-type clad layer, not only a p-type dopant Zn but also Fe is doped. Its Zn concentration is 1.5×1018 cm?3 and the Fe concentration is 1.8×1017 cm?3. In a semi-insulating burying layer, Fe is doped as an impurity generating a deep acceptor level and the concentration thereof is 6.0×1016 cm?3. The Fe concentration in the p-type clad layer is thus three times higher than the Fe concentration in the burying layer.Type: ApplicationFiled: March 21, 2008Publication date: October 2, 2008Applicants: FUJITSU LIMITED, EUDYNA DEVICES INC.Inventors: Kan TAKADA, Mitsuru EKAWA, Tsuyoshi YAMAMOTO, Tatsuya TAKEUCHI
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Publication number: 20060219996Abstract: In order to prevent As/P replacement at the boundary face of a re-grown semiconductor layer and avoid a crystalline defect caused by the replacement, there is provided an optical semiconductor device comprising: a semiconductor substrate; a striped stacking body including a first semiconductor layer, an active layer, and a second semiconductor layer; and a burying layer burying the striped stacking body striped stacking body, wherein surfaces in contact with a side face and a bottom face of the burying layer are made of a compound semiconductor that contains arsenic (As) alone as a group V element, and a portion other than the surface includes a group V element other than arsenic.Type: ApplicationFiled: October 6, 2005Publication date: October 5, 2006Inventors: Tsuyoshi Yamamoto, Mitsuru Ekawa
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Patent number: 6853661Abstract: A low clad layer made of semiconductor of a first conductivity type is formed on a semiconductor substrate. An active layer is formed on the low clad layer. The active layer is constituted by alternately stacking a strained well layer and a barrier layer. A partial or whole thickness of the active layer is periodically removed along a first direction parallel to the surface of the semiconductor substrate to form a diffraction grating. A filler made of semiconductor is embedded in the removed region. Strain of the strained well layer and strain of the filler have the same sign. An upper clad layer is formed on the active layer and filler and made of semiconductor of a second conductivity type. A semiconductor laser device is provided which has a smaller shift of spontaneous emission or PL even if a diffraction grating is formed in an active layer.Type: GrantFiled: February 14, 2003Date of Patent: February 8, 2005Assignee: Fujitsu LimitedInventor: Mitsuru Ekawa
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Publication number: 20030198266Abstract: A low clad layer made of semiconductor of a first conductivity type is formed on a semiconductor substrate. An active layer is formed on the low clad layer. The active layer is constituted by alternately stacking a strained well layer and a barrier layer. A partial or whole thickness of the active layer is periodically removed along a first direction parallel to the surface of the semiconductor substrate to form a diffraction grating. A filler made of semiconductor is embedded in the removed region. Strain of the strained well layer and strain of the filler have the same sign. An upper clad layer is formed on the active layer and filler and made of semiconductor of a second conductivity type. A semiconductor laser device is provided which has a smaller shift of spontaneous emission or PL even if a diffraction grating is formed in an active layer.Type: ApplicationFiled: February 14, 2003Publication date: October 23, 2003Applicant: FUJITSU LIMITEDInventor: Mitsuru Ekawa
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Patent number: 6376338Abstract: A first layer of InP is deposited on a diffraction grating so as to cover it, by MOCVD in which PH3 or organophosphorus is used as a source material of P and in which H2 is used as a carrier gas. The substrate is heated up to a temperature which is higher than the substrate temperature during the first layer deposition, and then a second layer is deposited on the first layer. An active layer is deposited on the second layer. Found out is such a growth rate of an InP layer as to cause the photoluminescence intensity of a layer corresponding to the active layer to be one tenth as small as that when the InP layer is deposited at a growth rate of 0.Type: GrantFiled: January 8, 1999Date of Patent: April 23, 2002Assignee: Fujitsu LimitedInventors: Mitsuru Ekawa, Takuya Fujii, Yuji Kotaki, Manabu Matsuda
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Patent number: 6238943Abstract: An optical semiconductor device of the present invention is provided with a core layer having a quantum well layer in that film thickness gets thinner from a inner region to an end portion in an optical waveguide region.Type: GrantFiled: September 22, 1999Date of Patent: May 29, 2001Assignee: Fujitsu LimitedInventors: Hirohiko Kobayashi, Mitsuru Ekawa, Nirou Okazaki, Shouichi Ogita, Haruhisa Soda, Haruhiko Tabuchi, Takuya Fujii
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Publication number: 20010001734Abstract: A first layer of InP is deposited on a diffraction grating so as to cover it, by MOCVD in which PH3 or organophosphorus is used as a source material of P and in which H2 is used as a carrier gas. The substrate is heated up to a temperature which is higher than the substrate temperature during the first layer deposition, and then a second layer is deposited on the first layer. An active layer is deposited on the second layer. Found out is such a growth rate of an InP layer as to cause the photoluminescence intensity of a layer corresponding to the active layer to be one tenth as small as that when the InP layer is deposited at a growth rate of 0.Type: ApplicationFiled: January 8, 1999Publication date: May 24, 2001Inventors: MITSURU EKAWA, TAKUYA FUJII, YUJI KOTAKI, MANABU MATSUDA
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Patent number: 6034983Abstract: A fabricating method of compound semiconductor device is proposed which has a step of varying selective growth ratio of crystal by changing either a mean free path of material gas in gas atmosphere for use in crystal growth or a thickness of a stagnant layer of the material gas, using selective growth mask having opening portion consisting of first region having a narrow width and second region having a wide width.Type: GrantFiled: April 29, 1998Date of Patent: March 7, 2000Assignee: Fujitsu LimitedInventors: Takuya Fujii, Mitsuru Ekawa, Tsuyoshi Yamamoto, Hirohiko Kobayashi