Abstract: A shot peening apparatus 1 includes: a storage container 2 that stores therein shots B impacting on a shot-peening treated region U; a vibrator 5 that accelerates the shots B; a shot outlet 4 that is formed on the storage container 2, and connected to a shot collecting passage 10 through which the shots B in a container inside 2I are collected, and through which the shots B are taken out from the container inside 2I into the shot collecting passage 10; and a shot inlet 3 that is formed on the storage container 2, and connected to a shot supplying passage 9 through which the shots B are supplied into the container inside 2I, and through which the shots B are supplied into the container inside 2I from the shot supplying passage 9.

Abstract: A layout method, upon performing layout of layer blocks each including internal elements, with respect to mounting area where internal element resources, to which internal elements can be assigned, are arranged, comprises: arranging, when first layer block and second layer block overlap in overlapping area, first layer block and the second layer block such that sum of number of first internal elements included in the overlapping area, among internal elements of first layer block, and number of second internal elements included in the overlapping area, among internal elements of second layer block, is not greater than number of internal element resources included in the overlapping area; and assigning the internal element resources included in the overlapping area to first layer block and second layer block, in accordance with ratio of number of first internal elements to number of second internal elements.

Abstract: A layout method in accordance with an exemplary aspect of the present invention performs layout of a semiconductor integrated circuit, the layout method including: performing logic synthesis without inserting at least one clock gating cell among clock gating cells inserted in the semiconductor integrated circuit; laying out a cell according to a result of the logic synthesis; inserting the clock gating cell not inserted in the logic synthesis after the cell is laid out; and laying out the inserted clock gating cell, and structuring a clock tree.

Abstract: A shot peening apparatus 1 includes: a storage container 2 that stores therein shots B impacting on a shot-peening treated region U; a vibrator 5 that accelerates the shots B; a shot outlet 4 that is formed on the storage container 2, and connected to a shot collecting passage 10 through which the shots B in a container inside 2I are collected, and through which the shots B are taken out from the container inside 2I into the shot collecting passage 10; and a shot inlet 3 that is formed on the storage container 2, and connected to a shot supplying passage 9 through which the shots B are supplied into the container inside 2I, and through which the shots B are supplied into the container inside 2I from the shot supplying passage 9.