Abstract: An IC layout system compiles a hierarchical netlist describing an IC into a database having a separate record for each cell and each module of the IC. Each database record references a cell library entry describing the cell or module and indicates a hierarchical relationship between its corresponding cell or module and other IC cells or modules. The system initially processes the database to reduce the number of cell and module records by combining hierarchically related cells and modules into larger cluster cells. The system then processes the database and cell library to generate a trial layout of the IC which positions highly interconnected cells near one another without regard to the hierarchical nature of the design.

Abstract: An integrated circuit (IC) layout process is organized into two phases. During the Phase 1 of the process, a preliminary placement plan is generated fixing the position of every cell of an IC design described by a gate level netlist. A trial routing plan is also generated establishing approximate routes of the nets that are to interconnect cell terminals. The placement plan and the trial routing plan are then iteratively analyzed and modified as necessary to ensure that the layout meets various signal path timing, signal integrity, and power distribution and other constraints. Thereafter, at the start of Phase 2 of the layout process, the trial routing plan is converted into a detailed routing plan specifying in detail the exact routes to be followed by all nets. The placement plan and detailed routing plan are then iteratively analyzed and modified as necessary to ensure that they meet all design constraints.

Abstract: Disclosed herein is a method for dividing an integrated circuit (IC) design into several circuit partitions, each including one or more circuit modules, and then separately carrying out placement and routing for each circuit partition, with each partition being implemented within a separate area of an IC substrate. The method initially generates a whole-chip trial placement that tends to cluster cells of each circuit module together. An IC substrate floor plan assigning modules to various partitions is prepared, with the size, shape and relative position of each partition being determined by size, shape and relative position of areas of the substrate occupied by those modules in the trial floor plan. A trial routing is also performed with information on which to base a pin assignment plan for each module. A detailed placement and routing process is then independently performed for each partition, with placement and routing of cells within each partition constrained by the floor plan and pin assignment plan.

Abstract: CAD software for automated circuit design provides improved display of hierarchical layout. Component placement perimeters are shown with “amoeba” characteristic for improved circuit floor-planning and analysis. Amoeba view of hierarchical design perimeter enables more intuitive observation of circuit floor-plan from actual component placement. Informational brevity conveyed by perimeters of hierarchies in design facilitates simpler interpretation of complex circuit layout, as well as distributed data access to remote sites through email or low-speed network.

Abstract: In computer-aided electronic design automation software, a placement system biases clustering of cells according to their hierarchical design while optimizing placement for controlling die size and total wire length. The placement system also provides for slack distribution, row improvement and randomization during partitioning. Floor plans based on trial placement and placement guiding blocks are also described.