Abstract: A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data.

Abstract: A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data.

Abstract: A memory circuit including memory elements on which the data read, write, and store operations can be arbitrarily performed, the memory elements having a dyadic/arithmetic operation function. In a read/modify/write mode to be executed during a memory cycle and in an interval in which data from the memory elements and data from external devices exist, an operation is executed between the external data and the data in the memory elements and the operation result is stored during a write cycle, thereby achieving a higher-speed operation.

Abstract: A memory circuit including memory elements on which data read, write and store operations can be arbitrarily performed, the memory elements having a dyadic/arithmetic operation function. In a read/modify/write mode to be executed during a memory cycle and in an interval in which data from the memory elements and data from external devices exist, an operation is executed between external data and the data in the memory elements and the result of such operation is stored during a write cycle, thereby achieving a higher-speed operation.

Abstract: A multipolar resolver is so constructed that the need of the conventionally indispensable coil on the resolver rotor is eliminated by providing a center coil on a stator, and 5n or 3n rotor poles and 4n stator poles are provided where n is a positive integer. Sine and consine coils are wound on the stator poles alternately, thus simplifying the construction of the multipolar resolver.

Abstract: A memory circuit including memory elements on which data read, write and store operations can be arbitrarily performed, the memory elements having a dyadic/arithmetic operation function. In a read/modify/write mode to be executed during a memory cycle and in an interval in which data from the memory elements and data from external devices exist, an operation is executed between external data and the data in the memory elements and the result of such operation is stored during a write cycle, thereby achieving a higher-speed operation.