Patents by Inventor Mitsuru Kaneda
Mitsuru Kaneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11158630Abstract: A semiconductor device includes an IGBT as a switching element, and a diode. The IGBT includes: a p type channel doped layer formed in a surface layer part on a front side of a semiconductor substrate; a p+ type diffusion layer and an n+ type source layer individually selectively formed in a surface layer part of the p type channel doped layer; and an emitter electrode connected to the n+ type source layer and the p+ type diffusion layer. A part of the p type channel doped layer reaches a front-side surface of the semiconductor substrate and is connected to the emitter electrode. On the front-side surface of the semiconductor substrate, the p+ type diffusion layer is interposed between the p type channel doped layer and an n+ type source layer, and the p type channel doped layer and the n+ type source layer are not adjacent to each other.Type: GrantFiled: September 13, 2019Date of Patent: October 26, 2021Assignee: Mitsubishi Electric CorporationInventors: Tetsuo Takahashi, Mitsuru Kaneda
-
Patent number: 10833574Abstract: A switching element control device for controlling a switching element incorporating a reverse conducting diode is provided. The switching element control device includes: a voltage detection circuit detecting a voltage across first and second main electrodes of the switching element; a comparator circuit comparing the voltage detected by the voltage detection circuit with a threshold voltage; and a drive circuit controlling driving of the switching element. The comparator circuit controls the drive circuit so that an on signal is not provided to the switching element when the detected voltage exceeds the threshold voltage.Type: GrantFiled: August 22, 2019Date of Patent: November 10, 2020Assignee: Mitsubishi Electric CorporationInventors: Mitsuru Kaneda, Tetsuo Takahashi, Shinya Soneda, Ryu Kamibaba
-
Publication number: 20200161459Abstract: A switching element control device for controlling a switching element incorporating a reverse conducting diode is provided. The switching element control device includes: a voltage detection circuit detecting a voltage across first and second main electrodes of the switching element; a comparator circuit comparing the voltage detected by the voltage detection circuit with a threshold voltage; and a drive circuit controlling driving of the switching element. The comparator circuit controls the drive circuit so that an on signal is not provided to the switching element when the detected voltage exceeds the threshold voltage.Type: ApplicationFiled: August 22, 2019Publication date: May 21, 2020Applicant: Mitsubishi Electric CorporationInventors: Mitsuru KANEDA, Tetsuo TAKAHASHI, Shinya SONEDA, Ryu KAMIBABA
-
Publication number: 20200135717Abstract: A semiconductor device includes an IGBT as a switching element, and a diode. The IGBT includes: a p type channel doped layer formed in a surface layer part on a front side of a semiconductor substrate; a p+ type diffusion layer and an n+ type source layer individually selectively formed in a surface layer part of the p type channel doped layer; and an emitter electrode connected to the n+ type source layer and the p+ type diffusion layer. A part of the p type channel doped layer reaches a front-side surface of the semiconductor substrate and is connected to the emitter electrode. On the front-side surface of the semiconductor substrate, the p+ type diffusion layer is interposed between the p type channel doped layer and an n+ type source layer, and the p type channel doped layer and the n+ type source layer are not adjacent to each other.Type: ApplicationFiled: September 13, 2019Publication date: April 30, 2020Applicant: Mitsubishi Electric CorporationInventors: Tetsuo TAKAHASHI, Mitsuru KANEDA
-
Patent number: 10593789Abstract: A semiconductor apparatus includes a semiconductor substrate including a semiconductor device. The semiconductor device includes a first n-type buffer layer, a second n-type buffer layer, and a first p-type semiconductor region. A first maximum peak concentration of first n-type carriers contained in the first n-type buffer layer is smaller than a second maximum peak concentration of second n-type carriers contained in the second n-type buffer layer. The first p-type semiconductor region is formed in the first n-type buffer layer. The first p-type semiconductor region has a narrower width than the first n-type buffer layer.Type: GrantFiled: August 30, 2018Date of Patent: March 17, 2020Assignee: Mitsubishi Electric CorporationInventors: Kenji Suzuki, Mitsuru Kaneda, Koichi Nishi
-
Patent number: 10347715Abstract: A semiconductor device includes a drift layer formed of a first conductive type semiconductor material, a MOSFET part including a p-type base layer provided on a front surface of the drift layer, a first n-type buffer layer provided on a reverse side of the drift layer, and a second n-type buffer layer provided on a reverse side of the first n-type buffer layer and having a high impurity concentration. The first n-type buffer layer has a higher impurity concentration than the drift layer and has a total amount of electrically active impurities per unit area of 1.0×1012 cm?2 or less.Type: GrantFiled: July 12, 2017Date of Patent: July 9, 2019Assignee: Mitsubishi Electric CorporationInventors: Kenji Suzuki, Tetsuo Takahashi, Mitsuru Kaneda, Ryu Kamibaba, Koichi Nishi
-
Patent number: 10263102Abstract: An object of the present invention is to provide a semiconductor device capable of preventing an occurrence of oscillation of voltage and current and a method of manufacturing the same. A semiconductor device according to the present invention includes an n type silicon substrate and a first n type buffer layer formed in a back surface of the n type silicon substrate and having a plurality of peaks of concentration of protons whose depths from the back surface are different from each other. In the first n type buffer layer, a concentration gradient of the protons from the peak located in a position closer to the back surface toward the surface of the n type silicon substrate is smaller than a concentration gradient of the protons from the peak located in a position farther away from the back surface toward the surface.Type: GrantFiled: February 16, 2018Date of Patent: April 16, 2019Assignee: Mitsubishi Electric CorporationInventors: Kenji Suzuki, Mitsuru Kaneda, Koichi Nishi, Katsumi Nakamura
-
Publication number: 20190103479Abstract: A semiconductor apparatus includes a semiconductor substrate including a semiconductor device. The semiconductor device includes a first n-type buffer layer, a second n-type buffer layer, and a first p-type semiconductor region. A first maximum peak concentration of first n-type carriers contained in the first n-type buffer layer is smaller than a second maximum peak concentration of second n-type carriers contained in the second n-type buffer layer. The first p-type semiconductor region is formed in the first n-type buffer layer. The first p-type semiconductor region has a narrower width than the first n-type buffer layer.Type: ApplicationFiled: August 30, 2018Publication date: April 4, 2019Applicant: Mitsubishi Electric CorporationInventors: Kenji Suzuki, Mitsuru Kaneda, Koichi Nishi
-
Patent number: 10205013Abstract: A semiconductor switching element includes a first gate electrode and a second gate electrode. The first gate electrode is disposed, via a first gate insulating film, inside a first trench that extends from an upper surface of an emitter region to reach a semiconductor layer, and intersects with the emitter region, a base region, and a charge storage layer. The second gate electrode is disposed, via a second gate insulating film, inside a second trench that extends from the upper surface of the emitter region and an upper surface of a conductive region to reach the semiconductor layer, and is adjacent to the emitter region, the base region, the charge storage layer, and the conductive region. The second trench is smaller in depth than the first trench, and the second trench is smaller in width than the first trench.Type: GrantFiled: December 18, 2017Date of Patent: February 12, 2019Assignee: Mitsubishi Electric CorporationInventors: Mitsuru Kaneda, Tetsuo Takahashi, Kenji Suzuki, Ryu Kamibaba, Mariko Umeyama, Koichi Nishi
-
Publication number: 20180366566Abstract: An object of the present invention is to provide a semiconductor device capable of preventing an occurrence of oscillation of voltage and current and a method of manufacturing the same. A semiconductor device according to the present invention includes an n type silicon substrate and a first n type buffer layer formed in a back surface of the n type silicon substrate and having a plurality of peaks of concentration of protons whose depths from the back surface are different from each other. In the first n type buffer layer, a concentration gradient of the protons from the peak located in a position closer to the back surface toward the surface of the n type silicon substrate is smaller than a concentration gradient of the protons from the peak located in a position farther away from the back surface toward the surface.Type: ApplicationFiled: February 16, 2018Publication date: December 20, 2018Applicant: Mitsubishi Electric CorporationInventors: Kenji SUZUKI, Mitsuru KANEDA, Koichi NISHI, Katsumi NAKAMURA
-
Publication number: 20180308963Abstract: A semiconductor switching element includes a first gate electrode and a second gate electrode. The first gate electrode is disposed, via a first gate insulating film, inside a first trench that extends from an upper surface of an emitter region to reach a semiconductor layer, and intersects with the emitter region, a base region, and a charge storage layer. The second gate electrode is disposed, via a second gate insulating film, inside a second trench that extends from the upper surface of the emitter region and an upper surface of a conductive region to reach the semiconductor layer, and is adjacent to the emitter region, the base region, the charge storage layer, and the conductive region. The second trench is smaller in depth than the first trench, and the second trench is smaller in width than the first trench.Type: ApplicationFiled: December 18, 2017Publication date: October 25, 2018Applicant: Mitsubishi Electric CorporationInventors: Mitsuru KANEDA, Tetsuo TAKAHASHI, Kenji SUZUKI, Ryu KAMIBABA, Mariko UMEYAMA, Koichi NISHI
-
Publication number: 20180130875Abstract: A semiconductor device includes a drift layer formed of a first conductive type semiconductor material, a MOSFET part including a p-type base layer provided on a front surface of the drift layer, a first n-type buffer layer provided on a reverse side of the drift layer, and a second n-type buffer layer provided on a reverse side of the first n-type buffer layer and having a high impurity concentration. The first n-type buffer layer has a higher impurity concentration than the drift layer and has a total amount of electrically active impurities per unit area of 1.0×1012 cm?2 or less.Type: ApplicationFiled: July 12, 2017Publication date: May 10, 2018Applicant: Mitsubishi Electric CorporationInventors: Kenji SUZUKI, Tetsuo TAKAHASHI, Mitsuru KANEDA, Ryu KAMIBABA, Koichi NISHI
-
Publication number: 20170294527Abstract: An insulated gate bipolar transistor (IGBT) includes: a p base layer disposed close to a front surface of an n-type silicon substrate; and a deep n+ buffer layer and a shallow n+ buffer layer disposed close to a back surface of the n-type silicon substrate. The p base layer has a higher impurity concentration than the n-type silicon substrate. The deep n+ buffer layer and shallow n+ buffer layer have higher impurity concentrations than the n-type silicon substrate. The deep n+ buffer layer is disposed throughout a region close to the back surface in the n-type silicon substrate. The shallow n+ buffer layer is selectively disposed close to the back surface in the n-type silicon substrate. The shallow n+ buffer layer has a higher impurity concentration than the deep n+ buffer layer, and is shallower from the back surface than the deep n+ buffer layer.Type: ApplicationFiled: December 13, 2016Publication date: October 12, 2017Applicant: Mitsubishi Electric CorporationInventors: Kenji SUZUKI, Tetsuo TAKAHASHI, Mitsuru KANEDA, Ryu KAMIBABA
-
Patent number: 7705398Abstract: A second impurity region is surrounded by a first impurity region at a first main surface. A third impurity region of the first main surface sandwiches the second impurity region with the first impurity region. Fourth and fifth impurity regions of a second main surface sandwich the first impurity region with the second impurity region. A control electrode layer is opposite to the second impurity region with an insulating film interposed. That portion of the second main surface which is opposite to the portion of the first main surface where the first impurity region is formed surrounds the regions for forming the fourth and fifth impurity regions of the second main surface, and it is a region of the first conductivity type or a region of the second conductivity type having impurity concentration not higher than that of the first impurity region.Type: GrantFiled: December 29, 2006Date of Patent: April 27, 2010Assignee: Mitsubishi Electric CorporationInventors: Mitsuru Kaneda, Hideki Takahashi, Yoshifumi Tomomatsu
-
Patent number: 7452756Abstract: The semiconductor device according to one of the aspects of the present invention includes a semiconductor substrate of a first conductivity type, having upper and lower surfaces. A collector region of a second conductivity type is formed on the lower surface of the semiconductor substrate, and a collector electrode is formed on the collector region. Also, at least one pair of isolation regions of the second conductivity type are formed extending from the upper surface of the semiconductor substrate to the collector layer for defining a drift region of the first conductivity type, in conjunction with the collector region. A base region of the second conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the drift region, and an emitter region of the first conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the base region. A gate electrode is formed opposing to the base region via an insulating layer.Type: GrantFiled: November 5, 2007Date of Patent: November 18, 2008Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Mitsuru Kaneda, Hideki Takahashi
-
Publication number: 20080093697Abstract: A second impurity region is surrounded by a first impurity region at a first main surface. A third impurity region of the first main surface sandwiches the second impurity region with the first impurity region. Fourth and fifth impurity regions of a second main surface sandwich the first impurity region with the second impurity region. A control electrode layer is opposite to the second impurity region with an insulating film interposed. That portion of the second main surface which is opposite to the portion of the first main surface where the first impurity region is formed surrounds the regions for forming the fourth and fifth impurity regions of the second main surface, and it is a region of the first conductivity type or a region of the second conductivity type having impurity concentration not higher than that of the first impurity region.Type: ApplicationFiled: December 29, 2006Publication date: April 24, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Mitsuru Kaneda, Hideki Takahashi, Yoshifumi Tomomatsu
-
Publication number: 20080064148Abstract: The semiconductor device according to one of the aspects of the present invention includes a semiconductor substrate of a first conductivity type, having upper and lower surfaces. A collector region of a second conductivity type is formed on the lower surface of the semiconductor substrate, and a collector electrode is formed on the collector region. Also, at least one pair of isolation regions of the second conductivity type are formed extending from the upper surface of the semiconductor substrate to the collector layer for defining a drift region of the first conductivity type, in conjunction with the collector region. A base region of the second conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the drift region, and an emitter region of the first conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the base region. A gate electrode is formed opposing to the base region via an insulating layer.Type: ApplicationFiled: November 5, 2007Publication date: March 13, 2008Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Mitsuru Kaneda, Hideki Takahashi
-
Patent number: 7326996Abstract: The semiconductor device according to one of the aspects of the present invention includes a semiconductor substrate of a first conductivity type, having upper and lower surfaces. A collector region of a second conductivity type is formed on the lower surface of the semiconductor substrate, and a collector electrode is formed on the collector region. Also, at least one pair of isolation regions of the second conductivity type are formed extending from the upper surface of the semiconductor substrate to the collector layer for defining a drift region of the first conductivity type, in conjunction with the collector region. A base region of the second conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the drift region, and an emitter region of the first conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the base region. A gate electrode is formed opposing to the base region via an insulating layer.Type: GrantFiled: October 11, 2005Date of Patent: February 5, 2008Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Mitsuru Kaneda, Hideki Takahashi
-
Publication number: 20060163664Abstract: The semiconductor device according to one of the aspects of the present invention includes a semiconductor substrate of a first conductivity type, having upper and lower surfaces. A collector region of a second conductivity type is formed on the lower surface of the semiconductor substrate, and a collector electrode is formed on the collector region. Also, at least one pair of isolation regions of the second conductivity type are formed extending from the upper surface of the semiconductor substrate to the collector layer for defining a drift region of the first conductivity type, in conjunction with the collector region. A base region of the second conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the drift region, and an emitter region of the first conductivity type is formed adjacent the upper surface of the semiconductor substrate and within the base region. A gate electrode is formed opposing to the base region via an insulating layer.Type: ApplicationFiled: October 11, 2005Publication date: July 27, 2006Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Mitsuru Kaneda, Hideki Takahashi
-
Patent number: 7009239Abstract: A semiconductor device includes an n-type semiconductor substrate (1) including a p-type collector layer (2) formed in a second main surface side thereof, a trench (13) is formed in a peripheral portion of the semiconductor substrate (1) so as to surround the inside and reach the collector layer (2) from a first main surface of the semiconductor substrate (1), and a p-type isolation region (14) formed by diffusion from a sidewall of the trench (13) is provided to be connected to the collector layer (2). The trench (13) is filled with a filling material (16).Type: GrantFiled: April 29, 2004Date of Patent: March 7, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Norifumi Tokuda, Tadaharu Minato, Mitsuru Kaneda