Patents by Inventor Mitsuru Kimura

Mitsuru Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220251639
    Abstract: An oligonucleotide includes an additional sequence for detecting a nucleic acid. At least one nucleotide in the additional sequence is modified with a photolabile protecting group.
    Type: Application
    Filed: May 19, 2020
    Publication date: August 11, 2022
    Inventors: Shinya OKI, Mitsuru Kimura
  • Publication number: 20200005167
    Abstract: The subconscious mind estimation system includes: an image display control unit 111 which causes an image display unit 13 to display first classification destination images 1211, 1212, 1213, and 1214, representing each of first type concepts and representing each of second type concepts, and first target images 1241 and 1251, corresponding to one of the first type concept and the second type concept; an operation trajectory recognition unit 112 which recognizes a first operation trajectory via an operation detection unit 14; and a subconscious mind estimation unit 113 which estimates the subconscious mind of the subject S about a tie between the first type concept and the second type concept based on the first operation trajectory.
    Type: Application
    Filed: March 11, 2016
    Publication date: January 2, 2020
    Inventors: Masahiro FUKUHARA, Kuniharu ARAMAKI, Yutaka KANOU, Mitsuru KIMURA
  • Patent number: 6746490
    Abstract: Disclosed are a winding method and structure for stator coils in which each stator coil is wound in series around a plurality of ones of coil bobbins fitted onto each stator tooth, whereby the number of coil end portions coming out from the stator coils is reduced, thereby achieving an improvement in terms of operational efficiency and reliability. In the winding method and structure for the stator coils, each stator coil is wound continuously and in series around a plurality of ones of the coil bobbins to form a series winding stator coil body, with a pair of coil ending portions coming from the ends of the series winding stator coil body.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: June 8, 2004
    Assignee: Tamagawa Seiki Kabushiki Kaisha
    Inventors: Mitsuru Kimura, Shigeru Nishida
  • Publication number: 20040031874
    Abstract: Disclosed are a winding method and structure for stator coils in which each stator coil is wound in series around a plurality of ones of coil bobbins fitted onto each stator tooth, whereby the number of coil end portions coming out from the stator coils is reduced, thereby achieving an improvement in terms of operational efficiency and reliability. In the winding method and structure for the stator coils, each stator coil is wound continuously and in series around a plurality of ones of the coil bobbins to form a series winding stator coil body, with a pair of coil ending portions coming from the ends of the series winding stator coil body.
    Type: Application
    Filed: August 13, 2002
    Publication date: February 19, 2004
    Applicant: TAMAGAWA SEIKI KABUSHIKI KAISHA
    Inventors: Mitsuru Kimura, Shigeru Nishida
  • Patent number: 5757062
    Abstract: A ceramic substrate for use with a semiconductor device, includes an electrical conductor composed of Ag, a resistor composed of oxide, and a barrier layer located between the electrical conductor and the resistor and composed of a material selected from a group consisting of AgPd and AgPt. The ceramic substrate prevents a diffusion of Ag atoms between the electrical conductor and the resistor, and hence provides a stable internal resistance.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: May 26, 1998
    Assignee: NEC Corporation
    Inventors: Kazuhiro Ikuina, Mitsuru Kimura
  • Patent number: 5728470
    Abstract: A multi-layer wiring substrate includes an insulating layer which is essentially formed of a silica sintered product, and a conductor layer formed on an upper surface of the insulating layer from an electrically conductive material. The multi-layer wiring substrate is produced by forming a green sheet from a starting powder such as an ultrafine powder of amorphous silica having an average particle size of several to tens nm, and firing or calcining the green sheet at a temperature of 800.degree. to 1,200.degree. C. in an atmosphere containing steam to provide a silica sintered product which is sintered to a sufficient extent and has a high strength. The starting powder has a composition which comprises 95.0 to 99.5% by weight of a fine silica powder, 0.05 to 5.0% by weight of an alkaline earth metal compound, or comprises 95.0 to 99.0% by weight of a fine silica powder and 1.0 to 5.0% by weight of B.sub.2 O.sub.3. The silica sintered product has a sufficiently high strength and a dielectric constant of 4.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: March 17, 1998
    Assignee: NEC Corporation
    Inventors: Ichiro Hazeyama, Kazuhiro Ikuina, Mitsuru Kimura
  • Patent number: 5714112
    Abstract: A process for producing a silica sintered product for a multi-layer wiring substrate of the invention includes: providing a fine silica powder having an average particle size of 5 to 500 nm and a fine crystallized quartz powder having an average particle size 1 to 10 .mu.m, the fine crystallized quartz powder having a volume equal to 1 to 20% of the entire volume of the fine silica powder and the fine crystallized quartz powder; mixing the fine silica powder and the fine crystallized quartz powder with a binder and a solvent to form a silica-containing slurry; forming a green sheet by slip-casting the silica-containing slurry; and firing the green sheet at a temperature of 800.degree. to 1200.degree. C. in an atmosphere containing steam at a partial pressure of 0.005 to 0.85 atm.
    Type: Grant
    Filed: December 5, 1995
    Date of Patent: February 3, 1998
    Assignee: NEC Corporation
    Inventors: Ichiro Hazeyama, Kazuhiro Ikuina, Mitsuru Kimura
  • Patent number: 5576518
    Abstract: A via-structure off a multilayer interconnection ceramic substrate for a multi-chip module, a semiconductor package and an insulating substrate has a high strength and a high reliability being produced at a low cost. A gap is provided at an interface between a via-conductor and ceramics, and filled with a resin. The resin is preferably of a thermosetting polyimide resin or a benzo-cyclo-butene resin.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: November 19, 1996
    Assignee: NEC Corporation
    Inventors: Akinobu Shibuya, Mitsuru Kimura
  • Patent number: 5545281
    Abstract: An integrated circuit connecting method that includes connecting electrode pads on an integrated circuit device to electrode terminals on a base with metal bumps interposed, the electrode terminals being formed in registry with the electrode pads.
    Type: Grant
    Filed: March 25, 1994
    Date of Patent: August 13, 1996
    Assignees: NEC Corporation, Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Koji Matsui, Mitsuru Kimura, Kazuaki Utsumi, Eiichi Ogawa, Hiroshi Komano, Toshimi Aoyama
  • Patent number: 5506058
    Abstract: A multilayer glass ceramic substrate includes a glass ceramic layer and a plurality of conductive layers laminated via the glass ceramic layer. The glass ceramic layer is composed of inorganic compound consisting of aluminum oxide, borosilicate glass, anorthite crystal and celsian crystal wherein the aluminum oxide is contained in the range of 12 to 59.6 weight percent, the borosilicate glass is contained in the range of 18 to 69.6 weight percent, the anorthite crystal is contained in the range of 1 to 40 weight percent and the celsian crystal is contained in the range of 1 to 5 weight percent so that the total is 100 weight percent.
    Type: Grant
    Filed: April 7, 1994
    Date of Patent: April 9, 1996
    Assignee: NEC Corporation
    Inventors: Kazuhiro Ikuina, Mitsuru Kimura
  • Patent number: 5485352
    Abstract: An element joining pad for a semiconductor device mounting board includes a thick-film metalized layer, a barrier layer, and a Ni plating layer. The thick-film metalized layer is selectively formed on a low-temperature sintered board and consists of one of a metal and an alloy which can be sintered at 500.degree. C. or more and 1,200.degree. C. or less. The barrier layer is formed on the thick-film metalized layer and constituted by one of a Rh plating layer and a Ru plating layer. The Ni plating layer is formed on the barrier layer.
    Type: Grant
    Filed: December 16, 1994
    Date of Patent: January 16, 1996
    Assignee: NEC Corporation
    Inventors: Akinobu Shibuya, Mitsuru Kimura
  • Patent number: 5318651
    Abstract: A method of bonding first and second circuit boards includes applying a light-sensitive adhesive over the first electrodes on a first circuit board and the areas where the first electrodes are not formed, and drying the applied adhesive to form a light-sensitive adhesive layer having the light-sensitive adhesive layer exposed selectively to active rays of light and performing development to remove only the light-sensitive adhesive layer on the first electrodes, and then performing a heat treatment to impart bonding quality to the light-sensitive adhesive layer remaining between adjacent first electrodes, placing the first and second circuit boards one on top of the other and thermocompressing the two circuit boards to have the first electrodes connected electrically to the second electrodes to form a single circuit board; and performing a heat treatment and/or exposure to active rays of light on the formed single circuit board.
    Type: Grant
    Filed: November 19, 1992
    Date of Patent: June 7, 1994
    Assignees: Nec Corporation, Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Koji Matsui, Mitsuru Kimura, Kazuaki Utsumi, Eiichi Ogawa, Hiroshi Komano, Toshimi Aoyama
  • Patent number: 4874721
    Abstract: A method for manufacturing a multichip package including the steps of forming a first polyimide insulating layer on a surface of a ceramic multilayer substrate having a circuit wiring therein, forming a first wiring connected to the circuit wiring of the multilayer substrate with a part of the first wiring being exposed at an open surface of the first polyimide insulating layer, forming a second polyimide insulating layer on a surface of a semiconductor element, and forming a second wiring connected with a circuit wiring of the semiconductor element in the second polyimide insulating layer with a part of the second wiring being exposed at an open surface of the second polyimide insulating layer.
    Type: Grant
    Filed: October 18, 1988
    Date of Patent: October 17, 1989
    Assignee: NEC Corporation
    Inventors: Mitsuru Kimura, Shoji Nakakita
  • Patent number: 4594473
    Abstract: A fine-wired conductor for use in LSI circuits exhibits good adhesion properties. The conductor is made up of a film of metal such as chrome or titanium on an insulator such as a ceramic substrate, a gold layer over the film of metal and a palladium film on the gold layer. In addition, a palladium layer can be interposed between the metal film and the gold layer to facilitate gold plating and inhibit diffusion of the metal and the gold.
    Type: Grant
    Filed: March 9, 1984
    Date of Patent: June 10, 1986
    Assignee: NEC Corporation
    Inventors: Tatsuo Inoue, Mitsuru Kimura