Abstract: A wireless communication monitoring system for monitoring a hardware failure of a wireless communication unit of a wireless communication device using a remote monitoring control device, in which the wireless communication device transmits or receives a predetermined radio signal to or from a monitoring device added or attached to the host device to perform a life and death check for checking an operation, and the remote monitoring control device detects a hardware failure of the wireless communication unit of the wireless communication device on the basis of a result of the life and death check received from the wireless communication device. This makes it possible to detect a failure that cannot be detected from information obtained from a device state request to a wireless communication device of the related art.

Abstract: An encryption device divides a message M into blocks of b bits, so as to generate data M[1], . . . , data M[m]. The encryption device sets data S0 of n=b+c bits to a variable S, updates the variable S by calculating a block cipher E using as input the variable S, then updates the variable S by calculating an exclusive OR using as input the variable S that has been updated and data X[i] that is data M[i] to which a bit string of c bits is added, and generates data C[i] by extracting b bits from the variable S that has been updated, for each integer i=1, . . . , m in ascending order. The encryption device generates a ciphertext C of the message M by concatenating the respective pieces of the data C[i] for each integer i=1, . . . , m. The encryption device extracts t bits from the variable S as an authenticator T, where t is an integer of 1 or greater.

Abstract: An encryption device divides a message M into blocks of b bits, so as to generate data M[1], . . . , data M[m]. The encryption device sets data S0 of n=b+c bits to a variable S, updates the variable S by calculating a block cipher E using as input the variable S, then updates the variable S by calculating an exclusive OR using as input the variable S that has been updated and data X[i] that is data M[i] to which a bit string of c bits is added, and generates data C[i] by extracting b bits from the variable S that has been updated, for each integer i=1, . . . , m in ascending order. The encryption device generates a ciphertext C of the message M by concatenating the respective pieces of the data C[i] for each integer i=1, . . . , m. The encryption device extracts t bits from the variable S as an authenticator T, where t is an integer of 1 or greater.

Abstract: The object is to enable cipher communication even when a cipher key in a one-time pad cipher (Vernam cipher) is running short. A one-time pad encrypting part encrypts communication data by the one-time pad cipher by sequentially using part of a one-time pad cipher key stored in a one-time pad cipher key storage part, to generate encrypted data. A block-encrypting part encrypts communication data by a block cipher by using a block-cipher key stored in a block-cipher key storage part, to generate encrypted data. An encryption control part controls whether the communication data is to be encrypted by the one-time pad encrypting part, or by the block-encrypting part, depending on a remaining bit count of the one-time pad cipher key stored in the one-time pad cipher key storage part.

Abstract: The object is to enable cipher communication even when a cipher key in a one-time pad cipher (Vernam cipher) is running short. A one-time pad encrypting part encrypts communication data by the one-time pad cipher by sequentially using part of a one-time pad cipher key stored in a one-time pad cipher key storage part, to generate encrypted data. A block-encrypting part encrypts communication data by a block cipher by using a block-cipher key stored in a block-cipher key storage part, to generate encrypted data. An encryption control part controls whether the communication data is to be encrypted by the one-time pad encrypting part, or by the block-encrypting part, depending on a remaining bit count of the one-time pad cipher key stored in the one-time pad cipher key storage part.

Abstract: A pseudo-random number generator 100 generates a pseudo-random number by the following operation. At C.2, S1[B41] is determined from B41 set in a second internal memory, and S2[B40] is determined from B40. Then, R[J] is generated from S1[I], S1[B41], and S2[B40]. At C.3, S1[I] is newly generated based on S1[B41] and S2[B40]. At C.4, B4 is updated from S2(I). In the above, the relationship between R[J] and S2(I) is cut off, which makes difficult to estimate S2(I) from R[J], and security is increased. Further, since S1[I], S1[B41], S2[B40], etc. have 4 bytes, the processing speed is high.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: A sub converter 330 provided in a data conversion apparatus for data encryption/decryption includes a data conversion function and a data transfer function or key transfer function, the sub converter converts data and transfers data that is nonlinear converted in a main converter 320 or a key that is outputted from a key KL register 240, by switching between the data conversion function and the data or key transfer function.

Abstract: A pseudo-random number generator 100 generates a pseudo-random number by the following operation. At C.2, S1[B41] is determined from B41 set in a second internal memory, and S2[B40] is determined from B40. Then, R[J] is generated from S1[I], S1[B41], and S2[B40]. At C.3, S1[I] is newly generated based on S1[B41] and S2[B40]. At C.4, B4 is updated from S2(I). In the above, the relationship between R[J] and S2(I) is cut off, which makes difficult to estimate S2(I) from R[J], and security is increased. Further, since S1[I], S1[B41], S2[B40], etc. have 4 bytes, the processing speed is high.

Abstract: In a data transformation apparatus for transforming two arbitrary pieces of data of A input data and B input data, a first nonlinear transformation of the A input data is performed using a first key parameter, a transformed result is output, an XOR operation of the transformed result and the B input data is performed to output an XORed result as B intermediate data, and the B intermediate data is input to a next sub-transformation unit as B input data. On the other hand, the B input data is input to a next sub-transformation unit as A input data. A second nonlinear transformation of the B input data is performed using a second key parameter, the transformed result is output, an XOR operation of the transformed result and the B intermediate data is performed to output an XORed result as B intermediate data, and the B intermediate data is input to a next sub-transformation unit as B input data.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit ((FL?1)) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit ((FL?1)) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: It is desired to share one circuit by an encryption unit 200 and a decryption unit 500. A normal data transformation unit (FL) 251 and an inverse data transformation unit (FL?1) 273 are located at point symmetry on a non-linear data transformation unit 220, and a normal data transformation unit (FL) 253 and an inverse data transformation unit (FL?1) 271 are located at point symmetry on the non-linear data transformation unit 220. Therefore, the encryption unit 200 and the decryption unit 500 can be configured using the same circuits.

Abstract: A sub converter 330 provided in a data conversion apparatus for data encryption/decryption includes a data conversion function and a data transfer function or key transfer function, the sub converter converts data and transfers data that is nonlinear converted in a main converter 320 or a key that is outputted from a key KL register 240, by switching between the data conversion function and the data or key transfer function.

Abstract: An integer Z101 is divided by an integer I102 to obtain a remainder R109. The integer I102 includes a polynomial of power of a basic operational unit of a computer. In this way, the integer I for divisor is limited based on the basic operational unit of the computer, thus a shift operation, which is required for a conventional operation method, can be eliminated. The remainder can be calculated by only addition and subtraction. Accordingly, a code size becomes compact and the remainder of the integer can be calculated at a high speed.