Patents by Inventor Mitsuru Nadaoka

Mitsuru Nadaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6199183
    Abstract: In a method of forming a scan path network, typical of the present invention, at a semiconductor integrated circuit having a clock node supplying a clock signal, a scan-in node supplying scan data and a scan-out node for receiving scan data outputted from scan flip-flops, the following steps are carried out. A plurality of scan flip-flops are placed. Delay times taken for the clock signal supplied to the clock node to reach the scan flip-flops are calculated. Distances between the scan flip-flops are calculated. Skews between the scan flip-flops are calculated. A sum of the calculated distances and the skews is calculated. The smallest value from within this total is then decided upon. The scan flip-flops are then connected across the scan-in node and the scan-out node based on this smallest value.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: March 6, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Mitsuru Nadaoka
  • Patent number: 5329162
    Abstract: A semiconductor device has a semiconductor substrate and a conductor layer provided over the semiconductor substrate. The conductor layer includes a first linear part extending in a first direction and provided with slits extending in the first direction, a second linear part extending in a second direction at an angle with the first direction and provided with slits extending in the second direction, and a junction part formed where the first and second linear parts are connected and provided with slits shorter than the slits in the first and second linear parts.
    Type: Grant
    Filed: June 17, 1992
    Date of Patent: July 12, 1994
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Mitsuru Nadaoka