Abstract: An array type semiconductor laser device includes: a second electrode (p-electrode) disposed on another conductivity type semiconductor layer; a third electrode (n-electrode) disposed on a one conductivity type semiconductor layer and between a first electrode (p-electrode) and the second electrode; a fifth electrode (n-electrode) disposed on the one conductivity type semiconductor layer and between the third electrode and the second electrode; a sixth electrode (n-electrode) disposed on the one conductivity type semiconductor layer and across from the fifth electrode; a first conductor (wire) that electrically connects the second electrode and the third electrode; and a second conductor (n-wiring) that electrically connects the fifth electrode and the sixth electrode.

Abstract: A semiconductor laser apparatus includes: a semiconductor laser device for junction down mounting that includes a first light-emitting device region and a second light-emitting device region formed separately on a substrate. The first light-emitting device region and the second light-emitting device region in the semiconductor laser device each have a stack structure in which an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are stacked in stated order. The first light-emitting device region includes a first electrode film located on the n-type semiconductor layer. The second light-emitting device region includes a second electrode film located on the p-type semiconductor layer. The first electrode film and the second electrode film are electrically connected to each other.

Abstract: A field effect transistor according to the present invention includes a channel layer formed above a semi-insulating substrate, a Schottky layer formed above the channel layer, a gate electrode formed on the Schottky layer, Ohmic contact layers that are located above the Schottky layer with the gate electrode interposed therebetween and formed of InGaAs, and a source electrode and a drain electrode that are formed on the Ohmic contact layers. The source electrode, the drain electrode and the gate electrode have a layered structure in which their corresponding layers are formed of the same material, a lowermost layer is a WSi layer and a layer containing Al is provided above the lowermost layer. A field effect transistor that has an electrode resistance equivalent to a conventional level and can reduce a cost of manufacturing a field effect transistor and a method for manufacturing the same are provided.

Abstract: A high frequency apparatus includes a dielectric substrate having a surface including a first area and at least one second area; a first dielectric thin layer provided on a portion of a first area; and a uniplanar transmission line provided on the first dielectric thin layer and on a portion of the second area, the uniplanar transmission line extending, continuously on the second area and the first dielectric thin layer.

Abstract: A high frequency apparatus includes a dielectric substrate having a surface including a first area and at least one second area; a first dielectric thin layer provided on a portion of a first area; and a uniplanar transmission line provided on the first dielectric thin layer and on a portion of the second area, the uniplanar transmission line extending, continuously on the second area and the first dielectric thin layer.

Abstract: A field-effect transistor of the present invention has first semiconductor layers disposed in at least two regions located above a substrate and spaced apart in a direction parallel to a substrate surface, second semiconductor layers disposed on the respective first semiconductor layers to protrude from the respective side surfaces of the first semiconductor layers, and ohmic electrodes disposed on the respective second semiconductor layers. The field-effect transistor also has a gate electrode formed by self alignment relative to the ohmic electrodes, which is disposed in a region located above the substrate and lying between the first semiconductor layers in spaced relation to the respective side surfaces of the first semiconductor layers.

Abstract: A method for fabricating a capacitor according to the present invention includes the steps of: forming a lower-level electrode layer over a structure having thermally deteriorative properties; depositing an insulating film, containing a titanium oxide, on the lower-level electrode layer at a deposition temperature of 400° C. or less; conducting a heat treatment at a temperature higher than the deposition temperature and lower than 500° C. after the insulating film has been deposited; and depositing an upper-level electrode layer on the insulating film after the heat treatment has been conducted.

Abstract: An organic polymer film patterning method includes the steps of: defining a resist film on a selected area of a substrate; depositing an organic polymer film over the substrate by a plasma CVD process so that the resist film is covered with part of the organic polymer film; and removing the resist film along with the part of the organic polymer film that has covered the resist film.

Abstract: First, an insulating film is formed over the entire surface of a semiconductor substrate including a channel region for a field effect transistor. The insulating film has a gate electrode opening over the channel region. Next, a protective film is deposited over the entire surface of the insulating film. Then, a lower electrode, a capacitive insulating film and an upper electrode are formed in this order in a region on the protective film where a capacitor will be formed. Subsequently, part of the protective film, with which the gate electrode opening of the insulating film has been filled in, is removed, thereby exposing the semiconductor substrate within the gate electrode opening. And then a gate electrode is formed to fill in the gate electrode opening again.

Abstract: An organic polymer film patterning method includes the steps of: defining a resist film on a selected area of a substrate; depositing an organic polymer film over the substrate by a plasma CVD process so that the resist film is covered with part of the organic polymer film; and removing the resist film along with the part of the organic polymer film that has covered the resist film.

Abstract: A heterojunction epitaxial layer, including a first semiconductor layer containing Al and having a thickness of 50 nm or less and a second semiconductor layer different in composition from the first semiconductor layer, is formed on a substrate composed of semi-insulating GaAs. A gate electrode is formed on a specified region of the top surface of the heterojunction epitaxial layer. The source/drain formation regions of the heterojunction epitaxial layer are provided with respective high-concentration N-type impurity diffusion regions, on which respective ohmic electrodes are formed.

Abstract: On a ceramic substrate, spiral-type inductors of a single layer wiring of a metal thin film are provided and respectively connected to a wiring pattern formed on another face of the substrate via through holes. A semiconductor chip is flip-chip mounted on the substrate in a face-down manner. On the face of the semiconductor chip, capacitors composed of a highly dielectric material, resistors formed by an ion implantation method or a thin-film forming method, and FETs are provided, respectively. Interconnection between the substrate and an external circuit board is achieved employing terminals formed at end faces of the substrate. The terminals have a concave shape with respect to the end face of the substrate. Thus, there is no need to use a package, and miniaturization and reduction in cost of a high-performance hybrid IC is achieved.

Abstract: On a semi-insulating substrate is formed a conductive layer and an undoped layer. On specified regions of the conductive layer are formed ohmic electrodes, each serving as a source electrode or a drain electrode, via a pair of square contact regions. The circumferential edges of the contact regions are undercut beneath the ohmic electrodes. Between the pair of contact regions on the conductive layer is formed a gate electrode by self alignment using the ohmic electrodes as a mask. The gate electrode has extended in the direction of gate width and the extended portion serves as a withdrawn portion of the gate electrode. Upper electrodes are formed by self alignment in the same process in which the gate electrode is formed.

Abstract: A method consists of the steps of depositing a Ti--Pt metal film on a SiN layer insulation film mounted on GaAs substrate, etching the Ti--Pt metal film to form a first metal layer, depositing a SrTiO.sub.3 insulating film, etching the SrTiO.sub.3 insulating film to form an insulating film, depositing a WSiN metal film according to a sputtering technique while controlling a deposition pressure of nitrogenous gas, etching the WSiN metal film to simultaneously form a second metal layer on the insulating film and a thin metal film resistive element on the SiN layer insulation film, depositing a SiO.sub.2 passivation film, and making via holes. SrTiO.sub.3 has a high relative dielectric constant, and WSiN has a high melting point. Nitrogen atoms in WSiN prevent oxygen atoms in the insulating film from diffusing into the second metal layer. The adhesion of second metal film to the insulating film is tight because of the sputtering technique.

Abstract: A capacitor element is formed in an integrated circuit having a compound semiconductor substrate such as a GaAs substrate and having Schottky type FETs formed on the substrate, with the capacitor element being formed by a process in which a lower electrode of a capacitor element and a lower layer portion of the gate electrode of a FET are formed by the same processing step from a high melting-point tungsten compound, a film of insulating material having a high dielectric coefficient is formed overall and is patterned to expose the gate electrode lower layer, and a high-conductance metallic film is then deposited overall and patterned to form an upper electrode of the capacitor element and an upper layer portion of the gate electrode. Capacitor elements and FETs can thereby be formed in such an IC by a simple process, while substantial reduction of the substrate area occupied by each capacitor element can be achieved.