Patents by Inventor Mitsuru Oida
Mitsuru Oida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8618657Abstract: A semiconductor device includes a semiconductor chip of a multilayer wiring structure having an insulating film formed on a surface thereof, multiple electrode pads formed at a central part and an outer peripheral part of the insulating film, and multiple protective metal layers formed respectively on the electrode pads. The semiconductor device also includes a substrate having the semiconductor chip mounted thereon and including multiple substrate terminals formed on a surface thereof respectively in positions corresponding to the electrode pads. The semiconductor chip is mounted on the substrate by connecting a stud bump to a solder bump. The stud bump is formed on any one of each of the protective metal layers and each of the substrate terminals and the solder bump is formed on the other one of each of the protective metal layers and each of the substrate terminals.Type: GrantFiled: August 5, 2009Date of Patent: December 31, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kiichiro Higaki, Koichi Sugihara, Katsuya Murakami, Shigenori Sawachi, Mitsuru Oida
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Publication number: 20100032833Abstract: A semiconductor device includes a semiconductor chip of a multilayer wiring structure having an insulating film formed on a surface thereof, multiple electrode pads formed at a central part and an outer peripheral part of the insulating film, and multiple protective metal layers formed respectively on the electrode pads. The semiconductor device also includes a substrate having the semiconductor chip mounted thereon and including multiple substrate terminals formed on a surface thereof respectively in positions corresponding to the electrode pads. The semiconductor chip is mounted on the substrate by connecting a stud bump to a solder bump. The stud bump is formed on any one of each of the protective metal layers and each of the substrate terminals and the solder bump is formed on the other one of each of the protective metal layers and each of the substrate terminals.Type: ApplicationFiled: August 5, 2009Publication date: February 11, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kiichiro Higaki, Koichi Sugihara, Katsuya Murakami, Shigenori Sawachi, Mitsuru Oida
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Patent number: 7148529Abstract: A semiconductor package includes (a) an interposer, (b) a wiring layer containing conductors formed adjacent to each other at intervals that cause no short circuit among the conductors, the wiring layer covering a given area of the interposer, to block light from passing through the given area, (c) a light blocking layer covering a no-wiring area of the interposer not covered by the wiring layer, to block light from passing through the no-wiring area, (d) a semiconductor chip electrically connected to the wiring layer, and (e) a resin mold sealing the wiring layer, the light blocking layer, and the semiconductor chip.Type: GrantFiled: March 20, 2002Date of Patent: December 12, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuru Oida, Masatoshi Fukuda, Yasuhiro Koshio, Hiroshi Funakura
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Patent number: 6960494Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.Type: GrantFiled: October 21, 2004Date of Patent: November 1, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
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Publication number: 20050051810Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.Type: ApplicationFiled: October 21, 2004Publication date: March 10, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
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Patent number: 6836012Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.Type: GrantFiled: March 29, 2002Date of Patent: December 28, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata
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Publication number: 20020140062Abstract: A semiconductor package includes (a) an interposer, (b) a wiring layer containing conductors formed adjacent to each other at intervals that cause no short circuit among the conductors, the wiring layer covering a given area of the interposer, to block light from passing through the given area, (c) a light blocking layer covering a no-wiring area of the interposer not covered by the wiring layer, to block light fiom passing through the no-wiring area, (d) a semiconductor chip electrically connected to the wiring layer, and (e) a resin mold sealing the wiring layer, the light blocking layer, and the semiconductor chip.Type: ApplicationFiled: March 20, 2002Publication date: October 3, 2002Applicant: KABUSHIKI KAISHA TOSHIBA.Inventors: Mitsuru Oida, Masatoshi Fukuda, Yasuhiro Koshio, Hiroshi Funakura
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Publication number: 20020140095Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.Type: ApplicationFiled: March 29, 2002Publication date: October 3, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Funakura, Eiichi Hosomi, Yasuhiro Koshio, Tetsuya Nagaoka, Junya Nagano, Mitsuru Oida, Masatoshi Fukuda, Atsushi Kurosu, Kaoru Kawai, Osamu Yamagata