Patents by Inventor Mitsuru Okazaki

Mitsuru Okazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9041160
    Abstract: A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: May 26, 2015
    Assignee: Rohm Co., Ltd.
    Inventors: Mitsuru Okazaki, Youichi Kajiwara, Naoki Takahashi, Akira Shimizu
  • Publication number: 20140299970
    Abstract: A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.
    Type: Application
    Filed: June 18, 2014
    Publication date: October 9, 2014
    Inventors: Mitsuru Okazaki, Youichi Kajiwara, Naoki Takahashi, Akira Shimizu
  • Patent number: 8786092
    Abstract: A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 22, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Mitsuru Okazaki, Youichi Kajiwara, Naoki Takahashi, Akira Shimizu
  • Publication number: 20120241969
    Abstract: A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.
    Type: Application
    Filed: September 22, 2011
    Publication date: September 27, 2012
    Applicant: ROHM CO., LTD.
    Inventors: Mitsuru OKAZAKI, Youichi KAJIWARA, Naoki TAKAHASHI, Akira SHIMIZU
  • Patent number: 7889467
    Abstract: In a protection circuit connected, via lines including an inductance component, to a circuit to be protected, a first transistor is arranged on a path to ground from a connection point of the protection circuit and the line. A second transistor is arranged on a path to ground from a connection point of the circuit to be protected and the line, and extracts, from a connection point, a current corresponding to a current flowing in the first transistor. The first and the second transistors are NPN bipolar transistors having a base and an emitter are commonly connected. A resistor is connected between the base and the emitter of the first transistor, and a diode is connected between the base and a collector.
    Type: Grant
    Filed: May 29, 2006
    Date of Patent: February 15, 2011
    Assignee: Rohm Co., Ltd.
    Inventors: Mitsuru Okazaki, Naoki Takahashi, Akira Shimizu, Kenichi Nakata
  • Publication number: 20090309117
    Abstract: In a protection circuit connected, via lines including an inductance component, to a circuit to be protected, a first transistor is arranged on a path to ground from a connection point of the protection circuit and the line. A second transistor is arranged on a path to ground from a connection point of the circuit to be protected and the line, and extracts, from a connection point, a current corresponding to a current flowing in the first transistor. The first and the second transistors are NPN bipolar transistors having a base and an emitter are commonly connected. A resistor is connected between the base and the emitter of the first transistor, and a diode is connected between the base and a collector.
    Type: Application
    Filed: May 29, 2006
    Publication date: December 17, 2009
    Applicant: ROHM CO., LTD.
    Inventors: Mitsuru Okazaki, Naoki Takahashi, Akira Shimizu, Kenichi Nakata
  • Publication number: 20090096107
    Abstract: In a semiconductor integrated circuit device, an element forming region and a metal wiring layer are covered with a passivation layer on a semiconductor substrate which is cut out in a rectangular shape. At four corners of the device, the passivation layer is provided with corner non-wiring regions formed directly on the semiconductor substrate. Thus, crack generation on the passivation layer due to heat stress can be suppressed.
    Type: Application
    Filed: June 13, 2006
    Publication date: April 16, 2009
    Applicant: Rohm Co., Ltd
    Inventors: Mitsuru Okazaki, Youichi Kajiwara, Naoki Takahashi, Akira Shimizu