Abstract: An object of the disclosure is to provide a semiconductor device having enhanced adhesion of the electrode while improving the reverse direction breakdown voltage, which is especially useful for power devices. A semiconductor device including a semiconductor layer and an electrode layer provided on the semiconductor layer and including at least a first electrode layer and a second electrode layer provided on the first electrode layer, wherein an outer edge portion of the second electrode layer is located outside an outer edge portion of the first electrode layer, wherein the semiconductor layer includes an electric field relaxation region with a different electrical resistivity from that of the semiconductor layer, and wherein the electric field relaxation region overlaps at least a part of a portion of the second electrode layer located outside the outer edge portion of the first electrode layer in plan view.

Abstract: Provided is a semiconductor device in which a leakage current is reduced, the semiconductor device which is particularly useful for power devices. A semiconductor device including at least: an n+-type semiconductor layer, which contains a crystalline oxide semiconductor as a major component; an n?-type semiconductor layer that is placed on the n+-type semiconductor layer, the n?-type semiconductor layer containing a crystalline oxide semiconductor as a major component; a high-resistance layer with at least a part thereof being embedded in the n?-type semiconductor layer, the high-resistance layer having a bottom surface located at a distance of less than 1.5 ?m from an upper surface of the n+-type semiconductor layer; and a Schottky electrode that forms a Schottky junction with the n?-type semiconductor layer, the Schottky electrode having an edge located on the high-resistance layer.

Abstract: Provided is a semiconductor device in which a leakage current is reduced, the semiconductor device which is particularly useful for power devices. A semiconductor device including at least: an n+-type semiconductor layer, which contains a crystalline oxide semiconductor as a major component; an n?-type semiconductor layer that is placed on the n+-type semiconductor layer, the n?-type semiconductor layer containing a crystalline oxide semiconductor as a major component; a high-resistance layer with at least a part thereof being embedded in the n?-type semiconductor layer, a depth d (?m) of the part embedded in the n?-type semiconductor layer satisfying d?1.4; and a Schottky electrode that forms a Schottky junction with the n?-type semiconductor layer, the Schottky electrode having an edge located on the high-resistance layer.

Abstract: Provided is a semiconductor element including: a multilayer structure including: a conductive substrate; and an oxide semiconductor film arranged directly on the conductive substrate or over the conductive substrate via a different layer, the oxide semiconductor film including an oxide, as a major component, having a corundum structure, the conductive substrate having a larger area than the oxide semiconductor film.

Abstract: Provided is a semiconductor element including: a multilayer structure including: a conductive substrate; and an oxide semiconductor film arranged directly on the conductive substrate or over the conductive substrate via a different layer, the oxide semiconductor film including an oxide, as a major component, containing gallium, the conductive substrate having a larger area than the oxide semiconductor film.

Abstract: An object of the disclosure is to provide a semiconductor device with low-loss and suppressed leakage current, which is particularly useful for power devices. A semiconductor device including a semiconductor layer, a dielectric film provided on the semiconductor layer and having an opening and provided over a distance of at least 0.25 ?m from the opening, and an electrode layer provided over a part or all of the dielectric film from the inside of the opening, wherein the dielectric film has a thickness of less than 50 nm from the opening to a distance of 0.25 ?m, and has relative permittivity of 5 or less.

Abstract: An object of the disclosure is to provide a semiconductor device with low-loss and suppressed leakage current, which is particularly useful for power devices. A semiconductor device including a semiconductor layer including an oxide semiconductor having a corundum structure as a main component, and a Schottky electrode including a first electrode layer and a second electrode layer having a higher conductivity than the first electrode layer, wherein an outer edge portion of the second electrode layer is electrically connected to the semiconductor layer at an electrical connection region through the first electrode layer, and an outer edge portion of the first electrode layer is located outside an outer edge portion of the electrical connection region.

Abstract: There is provided a crystalline film including, a crystalline metal oxide as a major component; a corundum structure; a dislocation density of 1×107 cm?2 or less; and a surface area of 10 mm2 or more. There is provided a method of producing a crystalline film comprising, forming a first lateral crystal growth layer on a substrate by first lateral crystal growth; placing a mask on the first lateral crystal growth layer; and forming a second lateral crystal growth layer by second lateral crystal growth.

Abstract: Provided is a semiconductor device in which crystal defects due to stress concentration in a semiconductor layer caused by an insulator film are prevented, the semiconductor device that is particularly useful for power devices. A semiconductor device including at least: a semiconductor layer; a Schottky electrode; and an insulator layer provided between a part of the semiconductor layer and the Schottky electrode, wherein the semiconductor layer contains a crystalline oxide semiconductor, and wherein the insulator layer has a taper angle of 10° or less.

Abstract: Provided are a multilayer structure in which crystal defects due to stress concentration in a semiconductor layer caused by an insulator film are prevented and a semiconductor device using the multilayer structure, the multilayer structure and the semiconductor device that are particularly useful for power devices. A multilayer structure in which an insulator film is arranged on a part of a semiconductor film, wherein the semiconductor film has a corundum structure and contains a crystalline oxide semiconductor containing one or two or more metals selected from groups 9 and 13 of the periodic table, and wherein the insulator film has a taper angle of 20° or less.

Abstract: An object of the disclosure is to provide a semiconductor device having enhanced adhesion of the electrode while improving the reverse direction breakdown voltage, which is especially useful for power devices. A semiconductor device including a semiconductor layer and an electrode layer provided on the semiconductor layer and including at least a first electrode layer and a second electrode layer provided on the first electrode layer, wherein an outer edge portion of the second electrode layer is located outside an outer edge portion of the first electrode layer, wherein the semiconductor layer includes an electric field relaxation region with a different electrical resistivity from that of the semiconductor layer, and wherein the electric field relaxation region overlaps at least a part of a portion of the second electrode layer located outside the outer edge portion of the first electrode layer in plan view.

Abstract: A semiconductor element and/or semiconductor device having enhanced semiconductor characteristics useful as power devices are provided. A semiconductor element, including: a first electrode; a second electrode; an n?-type semiconductor layer; and a low electrically conductive layer, the low electrically conductive layer that is arranged between the first electrode and the n?-type semiconductor layer, a first barrier height of the first electrode is larger than a second barrier height of the second electrode, a first electrical resistivity of the low electrically conductive layer is equal to or more than 1000 times as large as a second electrical resistivity of the n?-type semiconductor layer, and the semiconductor element that is configured to be able to irradiate light from an outside to at least a part of the low electrically conductive layer.

Abstract: In a first aspect of a present inventive subject matter, a semiconductor device includes a crystalline oxide semiconductor layer; and at least one electrode electrically connected to the crystalline oxide semiconductor layer. The crystalline oxide semiconductor layer includes at least one trench in the crystalline oxide semiconductor layer at a side of a first surface of the crystalline oxide semiconductor layer. The trench includes a bottom, a side, and at least one arc portion with a radius of curvature that is in a range of 100 nm to 500 nm, and the at least one arc portion is positioned between the bottom and the side, and an angle between the side of the trench and the first surface of the crystalline oxide semiconductor layer is 90° or more.

Abstract: A generation section generates a first display image based on an image signal output from an image pick-up device, and a second display image based on first and second image signals output from the image pick-up device. An identification section identifies an image region in the second display image generated by the generation section satisfying both a first condition and a second condition. The image region identified by the identification section is then displayed so as to be distinguishable from other regions in the second display image. The first condition indicates a condition of the magnitude of contrast being a first specific value or greater, and the second condition indicates a degree of matching between the first image and the second image being a second specific value or greater.

Abstract: An imaging element having a plurality of pixel cells which is arranged in a row direction and a column direction which is perpendicular to the row direction in a lattice, in which two adjacent pixel cells which include photoelectric convening units which detect the same color light form a pair and the pairs are periodically arranged, in each of pixel cell rows in which pixel cells are arranged in the row direction, the micro lenses are arranged such that the micro lenses in odd-numbered pixel cell rows is off-centered in the row direction from the micro lenses in even-numbered pixel cell rows by a half of an arrangement pitch of the micro lenses, and each micro lens which is provided in at least one of the odd-numbered row and the even-numbered row is disposed over two photoelectric converting units which detect different color light.

Abstract: A generation section generates a first display image based on an image signal output from an image pick-up device, and a second display image based on first and second image signals output from the image pick-up device. An identification section identifies an image region in the second display image generated by the generation section satisfying both a first condition and a second condition. The image region identified by the identification section is then displayed so as to be distinguishable from other regions in the second display image. The first condition indicates a condition of the magnitude of contrast being a first specific value or greater, and the second condition indicates a degree of matching between the first image and the second image being a second specific value or greater.

Abstract: A solid-state imaging device 5 is equipped with sets of pixel cells 53(1)-53(4), each set assuming a Bayer arrangement. A G pixel cell 53(2) is located right-adjacent to a G pixel cell 53(1). A G pixel cell 53(3) is located bottom-adjacent to the G pixel cell 53(2). A G pixel cell 53(4) is located right-adjacent to the G pixel cell 53(3).

Abstract: A color filter array has G filters, R filters, and B filters. A pair of phase difference pixels adjoining in a horizontal direction is provided with one of the G, R, and B filters. In the color filter array, a fundamental array pattern, including the G, R, and B filters, is repeatedly disposed in horizontal and vertical directions. The G filters, which most greatly contributes to obtainment of luminance information, are disposed in every line extending in the horizontal direction, the vertical direction, and slanting directions. Both of the R filters and the B filters are disposed in every line extending in the slanting directions. The number of the G filters is larger than that of the R filters or the B filters.

Abstract: A CCD image sensor, being a solid state imaging device, has four types of pixels, first to fourth pixels. The first to fourth pixels are arranged in a predetermined pattern. Each of the pixels has a PD and a microlens. Each of the microlens is arranged with its optical axis center eccentric or shifted in a predetermined direction from a center of a light receiving surface of the PD. A part of the microlens overlaps one or more adjacent pixels.

Abstract: An imaging element having a plurality of pixel cells which is arranged in a row direction and a column direction which is perpendicular to the row direction in a lattice, in which two adjacent pixel cells which include photoelectric convening units which detect the same color light form a pair and the pairs are periodically arranged, in each of pixel cell rows in which pixel cells are arranged in the row direction, the micro lenses are arranged such that the micro lenses in odd-numbered pixel cell rows is off-centered in the row direction from the micro lenses in even-numbered pixel cell rows by a half of an arrangement pitch of the micro lenses, and each micro lens which is provided in at least one of the odd-numbered row and the even-numbered row is disposed over two photoelectric converting units which detect different color light.