Abstract: The effect of timing inaccuracy is compensated for in a communication receiver that receives a transmission of bits temporally separated by a bit interval. The compensation employs an oversampling clock whose frequency defines a sampling interval that is smaller than the bit interval, which bit interval is nominally a predetermined integer multiple of the sampling interval. The oversampling clock samples the received transmission to produce an incoming sample stream. The incoming sample stream is decoded by a plurality of different decoding operations to produce, respectively, a plurality of decoded sample streams. It is determined whether the received transmission is decodable from any of the decoded sample streams.

Abstract: The effect of timing inaccuracy is compensated for in a communication receiver that receives a transmission of bits temporally separated by a bit interval. The compensation employs an oversampling clock whose frequency defines a sampling interval that is smaller than the bit interval, which bit interval is nominally a predetermined integer multiple of the sampling interval. The oversampling clock samples the received transmission to produce an incoming sample stream. The incoming sample stream is decoded by a plurality of different decoding operations to produce, respectively, a plurality of decoded sample streams. It is determined whether the received transmission is decodable from any of the decoded sample streams.

Abstract: A sequence of data samples and a sequence of non-data samples are provided. Four input samples from one of the data samples and the non-data samples are selected based on a clock signal. At least a portion of contents of a first group of memory cells are stored in a second group of memory cells. The first group of memory cells are comprised of four memory cells. The selected four input samples are stored in the first group of memory cells.

Abstract: A system and method is provided for processing four samples per clock period of an orthogonal frequency division multiplex symbol 10 having a length not a multiple of four. The method includes providing a sequence of data samples 12 and a sequence of non-data samples 14 and 16. The method includes selecting four input samples from one of the data samples 12 and the non-data samples 14 and 16 based on a clock signal. The method includes storing at least a portion of contents of a first group of memory cells 112 in a second group of memory cells 116. The first group of memory cells 112 comprised of four memory cells 112a-d. The method also provides for storing the selected four input samples in the first group of memory cells 112.

Abstract: To avoid a reduction in the efficiency of data transmission of a data processing device that conducts data communications using a serial bus that conforms to the IEEE 1394 Standards. The data processing device 1 has a calculator 9 and a comparator 8. The calculator 9 calculates the data volume of a response packet intended for reception that corresponds to a request packet intended for transmission when an attempt is made to transmit these packets, the comparator 8 compares the data volume of the response packet intended for reception and the empty volume of the receiving buffer 7, and when the empty volume of the receiving buffer 7 is smaller than the data volume of the response packet intended for reception, the packet transmitting device 3 does not transmits the request packet intended for transmission to the IEEE 1394 bus 6, and if the empty volume of the receiving buffer is too small and the response packet cannot be received, the request packet is not transmitted.

Abstract: Deter the lowering of the efficiency of data exchange in a data processing device that conducts data communications by using a serial bus conforming to the IEEF 1394 Standards.

Abstract: A FIFO is implemented as a buffer to encrypt/decrypt packet data and return the data to the same location where it was initially stored. No additional buffer or difficult buffer size decision is therefore required to compensate for the latency associated with the encryption/decryption. The FIFO implementation includes primary and secondary pointers. The primary pointers are available to the transmit/receive circuitry and the secondary pointers are used by the cryptographic circuit. When data is initially loaded into the FIFO, the FIFO does not report data availability to the primary user until the secondary user (cryptographic service) has read a block and returned the block to the same location. The FIFO is implemented via a single port RAM. Blocks are based on the encryption block size. The FIFO similarly reports packet availability based on application packet sizes (such as 188 MPEG2 transport stream packets).