Patents by Inventor Mitsuru SOMETANI

Mitsuru SOMETANI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12249625
    Abstract: A silicon carbide semiconductor device has an active region and a termination structure portion disposed outside of the active region. The silicon carbide semiconductor device includes a semiconductor substrate of a second conductivity type, a first semiconductor layer of the second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. During bipolar operation, a smaller density among an electron density and a hole density of an end of the second semiconductor layer in the termination structure portion is at most 1×1015/cm3.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: March 11, 2025
    Assignees: FUJI ELECTRIC CO., LTD., MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeshi Tawara, Tomonori Mizushima, Shinichiro Matsunaga, Kensuke Takenaka, Manabu Takei, Hidekazu Tsuchida, Kouichi Murata, Akihiro Koyama, Koji Nakayama, Mitsuru Sometani, Yoshiyuki Yonezawa, Yuji Kiuchi
  • Publication number: 20220123112
    Abstract: A silicon carbide semiconductor device has an active region and a termination structure portion disposed outside of the active region. The silicon carbide semiconductor device includes a semiconductor substrate of a second conductivity type, a first semiconductor layer of the second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. During bipolar operation, a smaller density among an electron density and a hole density of an end of the second semiconductor layer in the termination structure portion is at most 1×1015/cm3.
    Type: Application
    Filed: November 30, 2021
    Publication date: April 21, 2022
    Applicants: FUJI ELECTRIC CO., LTD., MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takeshi TAWARA, Tomonori MIZUSHIMA, Shinichiro MATSUNAGA, Kensuke TAKENAKA, Manabu TAKEI, Hidekazu TSUCHIDA, Kouichi MURATA, Akihiro KOYAMA, Koji NAKAYAMA, Mitsuru SOMETANI, Yoshiyuki YONEZAWA, Yuji KIUCHI
  • Patent number: 10755920
    Abstract: A method for manufacturing a semiconductor device includes: thermally-oxidizing a surface of a to-be-processed base made by SiC as body material to form a silicon dioxide film, by supplying gas containing oxidation agent to the surface of the to-be-processed base; exchanging ambient gas containing the oxidation agent after forming the silicon dioxide film, by decreasing a partial pressure of the oxidation agent in the ambient gas to 10 Pa or less; and after exchanging the ambient gas, lowering a temperature of the to-be-processed base.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: August 25, 2020
    Assignees: FUJI ELECTRIC CO., LTD., OSAKA UNIVERSITY
    Inventors: Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Mitsuru Sometani
  • Patent number: 10094867
    Abstract: A method of evaluating a semiconductor device having an insulated gate formed of a metal-oxide film semiconductor. The semiconductor device has a high potential side and a low potential side, and a threshold voltage that is a minimum voltage for forming a conducting path between the high and low potential sides. The method includes determining a variation of the threshold voltage at turn-on of the semiconductor device by continuously applying an alternating current (AC) voltage to the gate of the semiconductor device, a maximum voltage of the AC voltage being equal to or higher than the threshold voltage of the semiconductor device.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: October 9, 2018
    Assignees: FUJI ELECTRIC CO., LTD., National Institute of Advanced Industrial Science and Technology
    Inventors: Mitsuru Sometani, Manabu Takei, Shinsuke Harada
  • Patent number: 9805944
    Abstract: A p-type base region, n+-type source region, p+-type contact region, and n-type JFET region are formed on a front surface side of a silicon carbide base by ion implantation. The front surface of the silicon carbide base is thermally oxidized, forming a thermal oxide film. Activation annealing at a high temperature of 1500 degrees C. or higher is performed with the front surface of the silicon carbide base being covered by the thermal oxide film. The activation annealing is performed in a gas atmosphere that includes oxygen at a partial pressure from 0.01 atm to 1 atm and therefore, the thermal oxide film thickness may be maintained or increased without a decrease thereof. The thermal oxide film is used as a gate insulating film and thereafter, a poly-silicon layer that is to become a gate electrode is deposited on the thermal oxide film, forming a MOS gate structure.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: October 31, 2017
    Assignees: OSAKA UNIVERSITY, FUJI ELECTRIC CO., LTD.
    Inventors: Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Mitsuru Sometani
  • Publication number: 20170271168
    Abstract: A p-type base region, n+-type source region, p+-type contact region, and n-type JFET region are formed on a front surface side of a silicon carbide base by ion implantation. The front surface of the silicon carbide base is thermally oxidized, forming a thermal oxide film. Activation annealing at a high temperature of 1500 degrees C. or higher is performed with the front surface of the silicon carbide base being covered by the thermal oxide film. The activation annealing is performed in a gas atmosphere that includes oxygen at a partial pressure from 0.01 atm to 1 atm and therefore, the thermal oxide film thickness may be maintained or increased without a decrease thereof. The thermal oxide film is used as a gate insulating film and thereafter, a poly-silicon layer that is to become a gate electrode is deposited on the thermal oxide film, forming a MOS gate structure.
    Type: Application
    Filed: February 28, 2017
    Publication date: September 21, 2017
    Applicants: OSAKA UNIVERSITY, FUJI ELECTRIC CO., LTD.
    Inventors: Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Mitsuru SOMETANI
  • Publication number: 20170108545
    Abstract: A method of evaluating a semiconductor device having an insulated gate formed of a metal-oxide film semiconductor. The semiconductor device has a high potential side and a low potential side, and a threshold voltage that is a minimum voltage for forming a conducting path between the high and low potential sides. The method includes determining a variation of the threshold voltage at turn-on of the semiconductor device by continuously applying an alternating current (AC) voltage to the gate of the semiconductor device, a maximum voltage of the AC voltage being equal to or higher than the threshold voltage of the semiconductor device.
    Type: Application
    Filed: August 25, 2016
    Publication date: April 20, 2017
    Applicants: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Mitsuru SOMETANI, Manabu TAKEI, Shinsuke HARADA
  • Publication number: 20170069487
    Abstract: A method for manufacturing a semiconductor device includes: thermally-oxidizing a surface of a to-be-processed base made by SiC as body material to form a silicon dioxide film, by supplying gas containing oxidation agent to the surface of the to-be-processed base; exchanging ambient gas containing the oxidation agent after forming the silicon dioxide film, by decreasing a partial pressure of the oxidation agent in the ambient gas to 10 Pa or less; and after exchanging the ambient gas, lowering a temperature of the to-be-processed base.
    Type: Application
    Filed: July 27, 2016
    Publication date: March 9, 2017
    Applicants: OSAKA UNIVERSITY, FUJI ELECTRIC CO., LTD.
    Inventors: Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Mitsuru SOMETANI