Abstract: A microcomputer with a built-in flash memory is obtained in which the flash memory can be properly rewritten with a rewrite program kept placed on the flash memory and without requiring additional complicated control circuitry. On accepting an erase/write command which constitutes a rewrite command, a flash memory module (2) outputs to a flash memory control circuit (3) a ready status signal RYIBY indicative of a busy state during execution of the series of processing. When the ready status signal RYIBY indicates the busy state, the flash memory control circuit (3) outputs a hold signal HOLD at active “H,” in order to inhibit a CPU (1) from accessing the flash memory module (2). When the ready status signal RYIBY has recovered the ready state, the flash memory control circuit (3) outputs the hold signal HOLD at “L” to allow the CPU (1) to access the flash memory module (2).

Abstract: A bearing device for internal combustion engines, comprising a crankshaft of an internal combustion engine and bearings supporting the crankshaft, and wherein the crankshaft is made of steel having not been subjected to surface hardening and having a structure, which is mainly composed of pearlite having the pro-eutectoid ferrite fraction of at most 3%, and is processed to have the surface roughness Rz of at most 0.8 ?m, and wherein the bearings have an aluminum bearing alloy bonded to a back plate thereof and contain, as an alloy component thereof, at least Si particles of less than 4 mass %, whereby early abrasion and scratches of the crankshaft are suppressed to be equivalent to or less than abrasion loss and scratches of conventional DCI shafts.

Abstract: Redundant circuits 11 to 15 are provided in correspondence to memory blocks 1 to 5, respectively. Bit lines BL0 to BL15 are located across the memory blocks. Spare bit lines SBL1 and SBL2 are located across the redundant circuits 11 to 15. When a memory cell failure occurs in the memory block 5 except a predetermined memory block (for example, a boot block) 2 and when the bit line BL8 corresponding to the memory cell failure is replaced with the spare bit line SBL1, each of switches 56 and 76 is put into an on state in correspondence to the spare bit line SBL1. Furthermore, each of switches 48 and 88 is put into the on state in correspondence to the bit line BL8. As a result, the spare bit line SBL1 turns the redundant circuit 12 corresponding to the memory block 2, to be connected to the memory block 2.

Abstract: Defect information about a defective memory block is stored into a large capacity memory block having a low rewrite frequency and a block select circuit is provided that selects a backup memory block when the stored defect information is referred and the defective memory block is selected.

Abstract: A bearing device for internal combustion engines, comprising a crankshaft of an internal combustion engine and bearings supporting the crankshaft, and wherein the crankshaft is made of steel having not been subjected to surface hardening and having a structure, which is mainly composed of pearlite having the pro-eutectoid ferrite fraction of at most 3%, and is processed to have the surface roughness Rz of at most 0.8 &mgr;m, and wherein the bearings have an aluminum bearing alloy bonded to a back plate thereof and contain, as an alloy component thereof, at least Si particles of less than 4 mass %, whereby early abrasion and scratches of the crankshaft are suppressed to be equivalent to or less than abrasion loss and scratches of conventional DCI shafts.

Abstract: A half bearing constituting a cylindrical plain bearing for supporting a shaft for rotation when two of the half bearings are combined together. The half bearing has two circumferential ends each of which has a plurality of circumferential grooves without formation of any crush relief surface. The grooves extend substantially over an overall circumferential dimension of the half bearing and include portions located at both circumferential ends of the half bearing respectively. Each portion has a larger axially sectional area than the grooves formed in a portion of the half bearing mainly subjected to load during rotation of the shaft.

Abstract: Analog input selection circuits comprising an input terminal, an output terminal, a transmission path extending between the input terminal and the output terminal, transmission switches that open or close the transmission path, an over-voltage protection switch which connects or does not connect the transmission path to the ground, a PMOS transistor provided between the input terminal and a power supply, and an NMOS transistor provided between the input terminal and the ground are formed on an identical semiconductor substrate. If the semiconductor substrate is P-type, then a region in which the NMOS transistor is formed is surrounded by an N-well region.

Abstract: A microcomputer with a built-in flash memory is obtained in which the flash memory can be properly rewritten with a rewrite program kept placed on the flash memory and without requiring additional complicated control circuitry. On accepting an erase/write command which constitutes a rewrite command, a flash memory module (2) outputs to a flash memory control circuit (3) a ready status signal RYIBY indicative of a busy state during execution of the series of processing. When the ready status signal RYIBY indicates the busy state, the flash memory control circuit (3) outputs a hold signal HOLD at active “H,” in order to inhibit a CPU (1) from accessing the flash memory module (2). When the ready status signal RYIBY has recovered the ready state, the flash memory control circuit (3) outputs the hold signal HOLD at “L” to allow the CPU (1) to access the flash memory module (2).

Abstract: A semiconductor device of one chip has a first power supply terminal allowing connection with an external power supply IC, a second power supply terminal allowing connection with the external power supply IC, a main voltage dropping circuit connected with the first power supply terminal, a secondary voltage dropping circuit connected with the second power supply terminal, and an internal circuit connected with the main voltage dropping circuit and the secondary voltage dropping circuit. A high voltage of the external power supply IC is received in the main voltage dropping circuit through the first power supply terminal and is dropped. The high or low voltage of the external power supply IC is received in the secondary voltage dropping circuit through the second power supply terminal and is dropped. The internal circuit is operated by using the dropped voltage obtained in the main or secondary voltage dropping circuit.

Abstract: Defect information about a defective memory block is stored into a large capacity memory block having a low rewrite frequency and a block select circuit is provided that selects a backup memory block when the stored defect information is referred and the defective memory block is selected.

Abstract: Redundant circuits 11 to 15 are provided in correspondence to memory blocks 1 to 5, respectively. Bit lines BL0 to BL15 are located across the memory blocks. Spare bit lines SBL1 and SBL2 m are located across the redundant circuits 11 to 15. When a memory cell failure occurs in the memory block 5 except a predetermined memory block (for example, a boot block) 2 and when the bit line BL8 corresponding to the memory cell failure is replaced with the spare bit line SBL1, each of switches 56 and 76 is put into an on state in correspondence to the spare bit line SBL1. Furthermore, each of switches 48 and 88 is put into the on state in correspondence to the bit line BL8. As a result, the spare bit line SBL1 turns the redundant circuit 12 corresponding to the memory block 2, to be connected to the memory block 2.

Abstract: A half bearing constituting a cylindrical plain bearing for supporting a shaft for rotation when two of the half bearings are combined together. The half bearing has two circumferential ends each of which has a plurality of circumferential grooves without formation of any crush relief surface.

Abstract: A semiconductor device of one chip has a first power supply terminal allowing connection with an external power supply IC, a second power supply terminal allowing connection with the external power supply IC, a main voltage dropping circuit connected with the first power supply terminal, a secondary voltage dropping circuit connected with the second power supply terminal, and an internal circuit connected with the main voltage dropping circuit and the secondary voltage dropping circuit. A high voltage of the external power supply IC is received in the main voltage dropping circuit through the first power supply terminal and is dropped. A current supply capability and an electric power consumption rate in the secondary voltage dropping circuit are smaller than those of the main voltage dropping circuit, and the high voltage or a low voltage of the external power supply IC is received in the secondary voltage dropping circuit through the second power supply terminal and is dropped.

Abstract: A bearing structure with a low coefficient of friction and a distinguished wear resistance is obtained by coating a shaft with a resin composition comprising PAI and 5 to 50% by weight of PTFE, based on total resin composition and/or coating a bearing with a resin composition comprising PEEK and not more than 50% by weight of PTFE, based on total resin composition. By adding potassium titanate whiskers or a lead compound to the bearing resin composition, more improved coefficient of friction and wear resistance are obtained.

Abstract: A storage portion places data through a data output buffer on a data line D0.sub.P when a control line R00H becomes active, and places data through a data output buffer on a data line D0.sub.Q when a control line R03H becomes active. The storage portion further takes as input a signal on the data line D0.sub.P through a transmission gate when a control line W00H becomes active, and takes as input a signal on the data line D0.sub.Q through a transmission gate when a control line W003H becomes active. Thus, a storage device is provided to have the storage portion accessed by a plurality of access means at different addresses. It is thereby possible to select the optimal method of access to the storage portion, resulting in prevention of reduction of a program efficiency.

Abstract: An AD converting apparatus which is provided with a data update flag 3b for storing a first value ("1") when an analog signal is newly converted by an AD converter 1 to digital data and is stored into a data register 3a, and for storing a second value ("0") when the contents of the data register 3a are read out externally in a state under which the first value has been stored, and which eliminates a wasteful operation such that the data having already been used is used again to perform an arithmetic operation, by building in a hardware capable of indicating whether the data after AD conversion has already been used once or not, and thus improving processing speed as a whole; and a data processor in which the AD converting apparatus is built in.

Abstract: Disclosed is a bearing structure of a sliding bearing which is held in a housing and which rotatably supports a rotary shaft. At least one of the outer surface of the sliding bearing and the inner surface of the housing is covered with a coating layer which essentially consists of, by weight, a total amount of not more than 90% of solid lubricant and hard particles in which the solid lubricant is of 3 to 50% and the hard particles are of 1 to 50%, and the balance of polyamideimide resin.

Abstract: A wet friction member which can maintain boundary lubrication by decreasing the thickness of oil film on a friction surface even when the sliding velocity increases. In a case where the friction surface of the friction member is in pressure contact with a mated member while rotating in a state of boundary lubrications a shearing resistance owing to viscosity of cooling oil is circumferentially applied to cooling oil in outer grooves in the friction surface. Since outer grooves extend from starting position of intermediate portions of the friction surface and terminate at the outer peripheral edge in a volute shape toward the direction of rotation, cooling oil in the outer grooves flows along the groove walls and is quickly discharged from opening portions at the outer peripheral edge.

Abstract: A multiport memory includes a first memory block and a second memory block which are independently accessible with each other. Each of the first and second memory blocks can be accessed simultaneously through first and second ports. The memory includes a first access conflict detector for detecting an access conflict on the first memory block, a second access conflict detector for detecting an access conflict in the second memory block, a first arbitor responsive to the first detector for arbitrating an access conflict in the first memory block, and a second arbitor responsive to the second detector for arbitrating an access conflict in the second memory block. The memory further includes a selector for transferring the arbitration result of the first arbitor to the second memory block while neglecting the arbitration result of the second arbitor only when both the first and second detector detect the access confliction.

Abstract: A half bearing constituting a cylindrical plain bearing for supporting a shaft for rotation when two of the half bearings are combined together. The half bearing has two circumferential ends each of which has a plurality of circumferential grooves without formation of any crush relief surface. The grooves extend substantially over an overall circumferential dimension of the half bearing and include portions located at both circumferential ends of the half bearing respectively. Each portion has a larger axially sectional area than the grooves formed in a portion of the half bearing mainly subjected to load during rotation of the shaft.