Patents by Inventor Mitsuru Taguchi
Mitsuru Taguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240068881Abstract: A thermoelectric conversion device that includes an element body including a plurality of stacked; and a meandering wire inside the element body and that has a stacked structure. The meandering wire includes a thermoelectric material that has an anomalous Nernst effect, and a thermal conductivity of the plurality of stacked substrates is lower than that of the thermoelectric material. A thermoelectric conversion device that includes a winding core; and a winding wire wound around the winding core. The winding wire consists only of a thermoelectric material that has an anomalous Nernst effect. A thermoelectric conversion device that includes a plurality of substrates and meandering wires on main surfaces of the respective substrates. The meandering wires include a thermoelectric material that has an anomalous Nernst effect, and the substrates adjacent to each other are arranged at an angle that is larger than 0 degrees and smaller than 180 degrees.Type: ApplicationFiled: November 8, 2023Publication date: February 29, 2024Inventors: Eiichi MAEDA, Masashi HATTORI, Mitsuru ODAHARA, Toru TAKAHASHI, Kojiro KOMAGAKI, Takahiro TAGUCHI
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Patent number: 9206531Abstract: A method for producing an amylose-containing rayon fiber, comprising the steps of: mixing an aqueous alkaline solution of amylose with viscose to obtain a mixed liquid, spinning the mixed liquid to obtain an amylose-containing rayon fiber, and bringing the amylose-containing rayon fiber into contact with iodine or polyiodide ions, thereby allowing an amylose in the amylose-containing rayon fiber to make a clathrate including the iodine or polyiodide ions, wherein the amylose is an enzymatically synthesized amylose having a weight average molecular weight of 3×104 or more and 2×105 or less. A method for collecting iodine from brackish water with high efficiency utilizing the amylase-containing rayon fibers.Type: GrantFiled: June 17, 2010Date of Patent: December 8, 2015Assignees: Kanto Natural Gas Development Co., Ltd., Omikenshi Co., Ltd., Ezaki Glico Co., Ltd.Inventors: Osamu Inoue, Masatoshi Yoshikawa, Mieko Takaku, Tatsuo Kaiho, Mitsuru Taguchi, Haruyo Sambe, Yoshinobu Terada, Takeshi Takaha
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Publication number: 20120183491Abstract: A method for producing an amylose-containing rayon fiber, comprising the steps of: mixing an aqueous alkaline solution of amylose with viscose to obtain a mixed liquid, spinning the mixed liquid to obtain an amylose-containing rayon fiber, and bringing the amylose-containing rayon fiber into contact with iodine or polyiodide ions, thereby allowing an amylose in the amylose-containing rayon fiber to make a clathrate including the iodine or polyiodide ions, wherein the amylose is an enzymatically synthesized amylose having a weight average molecular weight of 3×104 or more and 2×105 or less. A method for collecting iodine from brackish water with high efficiency utilizing the amylase-containing rayon fibers.Type: ApplicationFiled: June 17, 2010Publication date: July 19, 2012Applicants: OMIKENSHI CO., LTD., KANTO NATURAL GAS DEVELOPMENT CO., LTD., EZAKI GLICO CO., LTD.Inventors: Osamu Inoue, Masatoshi Yoshikawa, Mieko Takaku, Tatsuo Kaiho, Mitsuru Taguchi, Haruyo Sambe, Yoshinobu Terada, Takeshi Takaha
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Patent number: 6878632Abstract: A semiconductor device capable of suppressing diffusion of copper at an interface between a copper wire and a cap film to enhance an electromigration resistance to ensure reliability of the copper wire, and a manufacturing method thereof are provided. The semiconductor device according to the present invention comprises an insulating film (12) formed on a substrate (11), a concave portion (13) (for example, a groove) formed in the insulating film, a conductive layer (15) embedded in the concave portion through a barrier layer (14), and a cobalt tungsten phosphorus coating (16) to connect with the barrier layer on the side of the conductive layer and to coat the conductive layer on the opening side of the concave portion.Type: GrantFiled: October 12, 2001Date of Patent: April 12, 2005Assignee: Sony CorporationInventors: Takeshi Nogami, Naoki Komai, Hideyuki Kito, Mitsuru Taguchi
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Publication number: 20040188273Abstract: An electrolytic polishing apparatus for electrolytic-polishing a conductive film subject to formed on a substrate including a resistance measuring unit for measuring the resistance of the film. The electrolytic polishing apparatus may also include a termination point detecting portion for detecting a termination point of polishing by reading a variation of the resistance value measured by the resistance measuring unit, or a polishing control portion for terminating electrolytic polishing on the basis of the termination point of polishing detected by the termination point detecting portion.Type: ApplicationFiled: April 13, 2004Publication date: September 30, 2004Inventors: Takeshi Nogami, Naoki Komai, Hideyuki Kito, Mitsuru Taguchi
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Patent number: 6736699Abstract: An electrolytic polishing apparatus for electrolytic-polishing a conductive film subject to formed on a substrate including a resistance measuring unit for measuring the resistance of the film. The electrolytic polishing apparatus may also include a termination point detecting portion for detecting a termination point of polishing by reading a variation of the resistance value measured by the resistance measuring unit, or a polishing control portion for terminating electrolytic polishing on the basis of the termination point of polishing detected by the termination point detecting portion.Type: GrantFiled: August 3, 2001Date of Patent: May 18, 2004Assignee: Sony CorporationInventors: Takeshi Nogami, Naoki Komai, Hideyuki Kito, Mitsuru Taguchi
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Patent number: 6709979Abstract: A method of implementing an electrolytic polishing process against a wiring-material film by way of preventing excessive polishing or incomplete polishing caused by presence of differential steps locally generated in the objective wiring-material film. The inventive method comprises a step of forming a wiring-material film for burying recessed portions formed on an insulating film formed on a substrate via a plating process; a step of reducing a local differential step generated on the surface of the wiring-material film by way of preserving the wiring material film on the insulating film; and a final step of removing the wiring-material film deposited on the insulating film by way of preserving such wiring-material film deposited, solely inside of the recessed portions.Type: GrantFiled: May 29, 2001Date of Patent: March 23, 2004Assignee: Sony CorporationInventors: Naoki Komai, Takeshi Nogami, Hideyuki Kito, Mitsuru Taguchi, Katsumi Ando
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Patent number: 6645852Abstract: A process for fabricating a semiconductor device, which comprises forming a recess portion in an insulating film covering a wiring made of copper or a copper alloy so that the recess portion reaches the wiring, wherein, after forming the recess portion, a plasma treatment using a gas containing hydrogen gas and nitrogen gas is conducted in a state such that the wiring is exposed through the bottom portion of the recess portion, or a plasma treatment using a gas containing hydrogen gas is conducted in a state such that the wiring is exposed through the bottom portion of the recess portion while cooling a substrate on which the wiring is formed. By the process of the present invention, a problem of redeposition of copper on the sidewall of a via hole in the argon sputtering and a problem of an etching process of the organic insulating film in the hydrogen plasma treatment can be solved, thus realizing excellent cleaning of the bottom portion of the via hole.Type: GrantFiled: October 17, 2000Date of Patent: November 11, 2003Assignee: Sony CorporationInventors: Mitsuru Taguchi, Shingo Kadomura, Miyata Koji
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Patent number: 6602787Abstract: The present invention is to provide a method for fabricating semiconductor devices capable of eliminating a height difference on a base member caused by a residual plating seed layer remained in a portion where an electrode comes into contact and is thus prevented from contacting with an electrolytic polishing fluid, where such height difference has been a problem in introducing the electrolytic polishing process into wafer process. The method comprises the steps of forming a plating seed layer on the base member; forming by the plating process a plated film on the plating seed layer in an area excluding the outer peripheral portion of the base member; polishing the plated film together with the plating seed layer by the electrolytic polishing process; and selectively removing the plating seed layer remaining on the outer peripheral portion of the base member.Type: GrantFiled: June 12, 2001Date of Patent: August 5, 2003Assignee: Sony CorporationInventors: Naoki Komai, Takeshi Nogami, Hideyuki Kito, Mitsuru Taguchi
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Patent number: 6593246Abstract: A process for producing a semiconductor device for forming a highly reliable wiring structure is provided that solves the problem occurring on using a xerogel or a fluorine resin in an inter level dielectric between the wirings to decrease a wiring capacitance, and the problem occurring on misalignment. A process for producing a semiconductor device comprising an inter level dielectric containing a xerogel film or a fluorine resin film comprises a step of forming, on the inter level dielectric comprising a lower layer of the inter level dielectric formed with an organic film and an upper layer of the inter level dielectric formed with a xerogel film or a fluorine resin film, a first mask to be an etching mask for forming a via contact hole by etching the inter level dielectric, and a step of forming, on the first mask, a second mask, which comprises a different material from the first mask, to be an etching mask for forming a wiring groove by etching the inter level dielectric.Type: GrantFiled: March 14, 2000Date of Patent: July 15, 2003Assignee: Sony CorporationInventors: Toshiaki Hasegawa, Mitsuru Taguchi, Koji Miyata
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Publication number: 20030119317Abstract: A semiconductor device capable of suppressing diffusion of copper at an interface between a copper wire and a cap film to enhance an electromigration resistance to ensure reliability of the copper wire, and a manufacturing method thereof are provided. The semiconductor device according to the present invention comprises an insulating film (12) formed on a substrate (11), a concave portion (13) (for example, a groove) formed in the insulating film, a conductive layer (15) embedded in the concave portion through a barrier layer (14), and a cobalt tungsten phosphorus coating (16) to connect with the barrier layer on the side of the conductive layer and to coat the conductive layer on the opening side of the concave portion.Type: ApplicationFiled: October 7, 2002Publication date: June 26, 2003Inventors: Takeshi Nogami, Naoki Komai, Hideyuki Kito, Mitsuru Taguchi
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Patent number: 6465342Abstract: The object of the invention is to solve failure in embedding conductive material by electroplating caused because organic insulating material is deformed by the compressive stress of a barrier metal layer such as tantalum nitride used for grooved interconnection, a groove-used for grooved interconnection is deformed and a seed layer is not fully formed in the groove and to enhance reliability upon interconnection. To achieve the object, a semiconductor device according to the invention is based upon a semiconductor device having a groove formed through a second insulating film over a substrate, a barrier metal layer formed at least on the inner wall of the groove and grooved interconnection embedded inside the groove via the barrier metal layer and is characterized in that a concave portion is continuously or intermittently formed along a groove through a second insulating film within a predetermined interval from grooved interconnection.Type: GrantFiled: March 13, 2000Date of Patent: October 15, 2002Assignee: Sony CorporationInventors: Mitsuru Taguchi, Naoki Komai
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Publication number: 20020090884Abstract: An electrolytic polishing apparatus for electrolytic-polishing a conductive film subject to formed on a substrate including a resistance measuring unit for measuring the resistance of the film. The electrolytic polishing apparatus may also include a termination point detecting portion for detecting a termination point of polishing by reading a variation of the resistance value measured by the resistance measuring unit, or a polishing control portion for terminating electrolytic polishing on the basis of the termination point of polishing detected by the termination point detecting portion.Type: ApplicationFiled: August 3, 2001Publication date: July 11, 2002Inventors: Takeshi Nogami, Naoki Komai, Hideyuki Kito, Mitsuru Taguchi
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Publication number: 20020074664Abstract: On a copper wiring surface, an oxidation resistive and fluorinated acid resistive layer is formed, and an oxidation resistive copper wiring, enhancement of resistive fluorinated acid nature are achieved. Furthermore, a via-hole connection resistance is reduced, and a clad layer (the CoWP layer) having oxidation resistive and fluorinated acid resistive nature high copper wiring configuration is formed, and cover layer (the CoWP layer) including cobalt and the CoWP layer of reliability, and the CoWP layer is formed by the copper wiring.Type: ApplicationFiled: July 25, 2001Publication date: June 20, 2002Inventors: Takeshi Nogami, Naoki Komai, Hideyuki Kito, Mitsuru Taguchi
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Publication number: 20020068438Abstract: The present invention is to provide a method for fabricating semiconductor devices capable of eliminating a height difference on a base member caused by a residual plating seed layer remained in a portion where an electrode comes into contact and is thus prevented from contacting with an electrolytic polishing fluid, where such height difference has been a problem in introducing the electrolytic polishing process into wafer process. The method comprises the steps of forming a plating seed layer on the base member; forming by the plating process a plated film on the plating seed layer in an area excluding the outer peripheral portion of the base member; polishing the plated film together with the plating seed layer by the electrolytic polishing process; and selectively removing the plating seed layer remaining on the outer peripheral portion of the base member.Type: ApplicationFiled: June 12, 2001Publication date: June 6, 2002Inventors: Naoki Komai, Takeshi Nogami, Hideyuki Kito, Mitsuru Taguchi
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Patent number: 6380065Abstract: In a related interconnection structure that is formed by filling a metal, there have been problems, since defective connection occurs due to generation of voids and other features caused by poor filling of the metal, which entails reduction in reliability, and contact resistance is large due to a barrier metal layer at a contact portion. A novel interconnection structure is provided which comprises: a recess (for example, a contact hole, a trench, or a trench and a contact hole formed at a bottom of the trench), which is connected onto a conductive material mass formed in an insulating film, and which is formed in the insulating film; a barrier metal layer formed on side walls of the recess; and metal material masses filled in the interior of the recess, wherein the metal material masses are formed with a metal repeatedly filled into the recess over a plurality of times, and a metal material mass and a conductive material mass are directly connected to each other.Type: GrantFiled: November 8, 1999Date of Patent: April 30, 2002Assignee: Sony CorporationInventors: Naoki Komai, Shingo Kadomura, Mitsuru Taguchi, Akira Yoshio, Takaaki Miyamoto
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Patent number: 6361662Abstract: Disclosed is a magnetron sputtering system enabling formation of a film of a ferroelectric substance by suppressing occurrence of a magnetic field due to an eddy current. The magnetron sputtering system includes a flat target; magnetic field applying means (magnets), provided in the vicinity of a back surface of the target, for applying a magnetic field to a front surface of the target; and magnetic field rotating means (motor) for rotating the magnetic field applying means so as to rotate the magnetic field applied to the front surface of the target. The magnetic field rotating means is provided with rotational speed varying means (speed controller) for varying the rotational speed of the magnetic field applied by the magnetic field rotating means.Type: GrantFiled: December 22, 1997Date of Patent: March 26, 2002Assignee: Sony CorporationInventors: Yasuhiro Chiba, Keiichi Maeda, Mitsuru Taguchi
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Publication number: 20020016064Abstract: A method of implementing an electrolytic polishing process against a wiring-material film by way of preventing excessive polishing or incomplete polishing caused by presence of differential steps locally generated in the objective wiring-material film. The inventive method comprises a step of forming a wiring-material film for burying recessed portions formed on an insulating film formed on a substrate via a plating process; a step of reducing a local differential step generated on the surface of the wiring-material film by way of preserving the wiring material film on the insulating film; and a final step of removing the wiring-material film deposited on the insulating film by way of preserving such wiring-material film deposited, solely inside of the recessed portions.Type: ApplicationFiled: May 29, 2001Publication date: February 7, 2002Inventors: Naoki Komai, Takeshi Nogami, Hideyuki Kito, Mitsuru Taguchi, Katsumi Ando
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Patent number: 6333258Abstract: A manufacturing method for forming a dual damascene structure in which the effective permittivity of an inter-layer insulating film is lowered without an etching mask for forming a contact hole, which is otherwise formed in the inter-layer insulating film. The manufacturing method comprises the step of forming an inorganic film to serve as an etching mask, on the inter-layer insulating film; the step of forming a first opening pattern for forming a wiring groove, in an upper part of the inorganic film; and the step of forming a second opening pattern for forming a contact hole, so as to coincide with the first opening pattern at least partially.Type: GrantFiled: March 23, 2000Date of Patent: December 25, 2001Assignee: Sony CorporationInventors: Koji Miyata, Toshiaki Hasegawa, Mitsuru Taguchi
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Patent number: RE40748Abstract: A process for producing a semiconductor device for forming a highly reliable wiring structure is provided that solves the problem occurring on using a xerogel or a fluorine resin in an inter level dielectric between the wirings to decrease a wiring capacitance, and the problem occurring on misalignment. A process for producing a semiconductor device comprising an inter level dielectric containing a xerogel film or a fluorine resin film comprises a step of forming, on the inter level dielectric comprising a lower layer of the inter level dielectric formed with an organic film and an upper layer of the inter level dielectric formed with a xerogel film or a fluorine resin film, a first mask to be an etching mask for forming a via contact hole by etching the inter level dielectric, and a step of forming, on the first mask, a second mask, which comprises a different material from the first mask, to be an etching mask for forming a wiring groove by etching the inter level dielectric.Type: GrantFiled: September 30, 2004Date of Patent: June 16, 2009Assignee: Sony CorporationInventors: Toshiaki Hasegawa, Mitsuru Taguchi, Koji Miyata