Abstract: A differential detection receiver with a reduced power consumption is provided by simplifying constituent circuits of the differential detection receiver. An arctangent calculator is realized without using an multiplier or a conversion table. Without using a D/A converter, a level adjusting circuit for adjusting the absolute value of a vector (Ax, Ay) given as input signals Ax and Ay so as to make it one. The power consumption of a differential detection demodulator is reduced by eliminating power consuming circuits such as a multiplier and a large conversion table from the system. There are disclosed some embodiments.

Abstract: Noise generating section 106 generates noise data of a white Gaussian noise, and noise adding section 107 adds received data and the noise data. Channel estimating section 108 performs channel estimation using the added data output from noise adding section 107. At this point, when a level of a preceding signal is equal to or less than that of the noise data, channel estimating section 108 is not capable of detecting the preceding signal. Accordingly, in the case where a received level of a preceding signal is extremely lower than that of a delayed signal and a noise level is further lower than the received level of the preceding signal, it is possible to perform pre-equalization using the delayed signal as a desired signal, whereby it is possible to maintain the reception characteristic of a communication partner.

Abstract: A signal received by a receiving antenna is input to an UDMV through a detector, and compensation for distortion caused by multipath fading and an error correction using Viterbi decoding are simultaneously performed, obtaining demodulation data. The UDMV comprises a demodulator in which an MLSE and a Viterbi decoder are combined. Thereby, equalization for removing a line distortion and reduction in an error rate can be simultaneously performed, improving a receiving quality.

Abstract: A CDMA radio transmission apparatus includes a multiplexer that time-multiplexes variable data and fixed data. The variable data includes a quantity of data that is variable with respect to time and the fixed data includes a quantity of data that is fixed with respect to time. A randomizer randomizes a transmission timing of the fixed data by controlling a placement of the fixed data. A data quantity converter that converts the quantity of variable data.

Abstract: Slot quality detector 121 detects reception level, and power controller inversely corresponding to reception quality 122 outputs power control information indicative of increasing transmission power in the case where the detected reception level is higher than a threshold value and of decreasing the transmission power in the case where the detected quality is lower than the threshold value. Transmission power setter 108 performs the setting of transmission power corresponding to the power control information and provides a control to transmit by the set power. That allows improving of a battery saving and moderating of the specification of amplifiers in a transmission/reception apparatus, thereby resulting in decreased interference to signals of other users in the CDMA communication.

Abstract: In a CDMA radio transmitting apparatus that controls generation of unnecessary frequency components, variable data, after assembled by frame assembly circuit in frame units, is time-multiplexed with fixed data in slot assembly circuit. At this time, slot assembly circuit reads the placement location information of fixed data in each slot from memory and carries out time-multiplexing based on the information using random patterns whose repetition cycle is one super frame.

Abstract: An improved antenna arrangement for use in a cellular telecommunication system is provided. A plurality of antennas which are connected to a common base station are located on the periphery of a radio zone or cell. Each of the antennas has a directional characteristic oriented toward the center of the cell to cover the inside of the cell. This antenna arrangement minimizes the co-channel interference, thereby allowing the distance between cells to which the same channel is assigned to be shortened.

Abstract: A synchronization equipment performs correlation processing between a first known pattern included in a received signal and a second known pattern, and detects reception timing of the received signal. A correlation value computing portion computes a correlation value between the first known pattern and the second known pattern at every reception time. A reception timing detection portion compares the computed related value with a predetermined threshold value, determines the reception time when the correlation value becomes larger than the threshold value to be the reception timing of a received signal, and, after this determination, suspends the comparison between the correlation value and the threshold value, and holds the reception time determined to be the reception timing.

Abstract: Slot quality detector 121 detects a reception level, and power controller inversely corresponding to reception quality 122 outputs power control information indicative of increasing transmission power in the case where the detected reception level is higher than a threshold value and of decreasing the transmission power in the case where the detected quality is lower than the threshold value. Transmission power setter 108 performs the setting of transmission power corresponding to the power control information and provides a control to transmit by the set power. That allows improving of a battery saving and moderating of the specification of amplifiers in a transmission/reception apparatus, thereby resulting in decreased interference to signals of other users in the CDMA communication.

Abstract: The present invention is characterized by that, at a reception section of a base station in a CDMA system including a reception antenna, a radio section and the number of demodulators corresponding to the number of users where spreading codes of a plurality of spreading factors are available, an algorithm diversity controller and a selector are prepared, information concerning spreading factors of spreading codes utilized by users and others are applied to the algorithm diversity controller, algorithm diversity controller instructs the number of demodulators prepared corresponding to the number of users and the selector, and when signals transmitted by a user utilizing a spreading code of a low spreading factor, i.e. signals with high symbol rate, are received, by demodulating signals with different reception methods or different parameters at demodulators leftover because of the low spreading factor, the demodulated signals of the best quality are selected.

Abstract: The synchronizing apparatus includes a block for detecting a code from an input signal, a block for detecting from the code the variable points of the code at several times as high as the symbol rate, a block for calculating a histogram of the detected variables of the code to time, and a block for deciding that the phase number at which the calculated histogram takes the maximum value is a symbol synchronization point. This synchronizing apparatus detects the zero-cross points of an intermediate frequency band signal at N times as high as the symbol rate. It also calculates a histogram of detected time (0 to N−1). The time (0 to N−1) at which the histogram is the maximum within a predetermined detected time is selected as a symbol clock, and thereby symbol synchronization is established.

Abstract: An estimator of error rate is provided for reducing variations of an error pulse count value at burst signals of a received signal for digital mobile communications and thereby improving an accuracy of estimating an error rate. The estimator of error rate includes detectors for detecting that phase information derived from a baseband signal of an I channel (I signal) and a baseband signal of a Q channel (Q signal) is located in an error pulse generation area, detectors for detecting that envelope information of the I signal and the Q signal is located in the error pulse generation area, and a counter for detecting that the phase error signal and the envelope error signal are outputted and counting the signals. The estimator operates to estimate an error rate based on an error pulse count value at one period. The estimator operates to detect that the phase information and the envelope information are located in the error pulse generation area.

Abstract: A plurality of amplifiers having different amplification factors are provided and a received signals and amplified output signal are all sampled by A/D converters. A selector selects, from the sampled signal, a signal from which accuracy can be attained exceedingly and is not saturated upon sampling, so that there can be provided an A/D conversion apparatus which does not require AGC control and conversion calculation of data and can obtain desired accuracy. Selection logic can use comparison of maximum values and logical sums of absolute values of the sampled values, levels which are not amplified or the like.

Abstract: A modulator and modulation method for orthogonally modulating digital baseband signals include interpolation filters that frequency convert the frequencies of an in-phase component and a quadrature phase component of a digital baseband signal to four times the frequency of an intermediate frequency. .DELTA..SIGMA. modulation circuits are provided and .DELTA..SIGMA. modulate the frequency converted signals. A low pass filter is provided to remove unnecessary components from the .DELTA..SIGMA. modulated signals. A switching circuit selects a signal that has passed through the low pass filter according to an order of an in-phase component, a code inverted component of a quadrature phase component, a code inverted component of the in-phase component and the quadrature phase component, and outputs these signals as a digital orthogonal signal. An N bit D/A converter converts the digital orthogonal signals into analog orthogonal signals.

Abstract: A differential detector imparted with error correcting function for detecting a differentially phase shifted signal while performing error correction includes a one-symbol differential detector for performing phase comparison between a current input signal and a signal preceding by one symbol, a delay circuit for delaying a one-symbol differential detection signal by two symbol periods, a two-symbol differential detector for performing phase comparison between the current input signal and an input signal preceding by two symbol periods, a four-symbol differential detector for performing phase comparison between the current input signal and an input signal preceding by four symbol periods, and two error correction circuits.

Abstract: A data receiving apparatus. A plurality of A/D converters are used to convert a received input signal into digital signals having different sampling phases. Each of the digital signals is demodulated, and applied to a discriminator for obtaining a logic state from the demodulated signal. The logic state derived from the discriminator is compared with the demodulated signal producing the logic signal in a comparing circuit to derive an error. An error comparing circuit compares each of the errors, and a data selector responds to the error comparing circuit to select the logic signal showing the smallest error as decoded data.

Abstract: An equalizer block forming part of a receiver compensates transmission path characteristics of a baseband received signal to generate a prediction signal, and differential-logic-converts a demodulated signal generated by demodulating the prediction signal to generate a differential-logic-conversion demodulated signal. A differential-detection demodulator block differential-detects the prediction signal from the equalizer block and subsequently demodulates the differential-detected prediction signal to generate a differential-detection demodulated signal. A selector block selects either the differential-logic-conversion demodulated signal from the equalizer block or the differential-detection demodulated signal from the difference-detection demodulator block.

Abstract: A differential detection receiver with a reduced power consumption is provided by simplifying constituent circuits of the differential detection receiver. An arctangent calculator is realized without using a multiplier of a conversion table. Without using a D/A converter, a level adjusting circuit for adjusting the absolute value of a vector (Ax, Ay) given as input signals Ax and Ay so as to make it one. The power consumption of a differential detection demodulator is reduced by eliminating power consuming circuits such as a multiplier and a large conversion table from the system.

Abstract: The interference signal cancellation system of the invention has: usual CDMA demodulators respectively disposed for codes, each of the CDMA demodulators having a matched filter 105 and an identifier 107; and a likelihood calculator 108 for each of the demodulators. The apparatus further has: a buffer 103 which stores provisional decision values; another buffer 109 which stores likelihoods; an order determining device 110 which determines an order in accordance with the likelihoods; a respreading device 111 which performs respreading in accordance with the determined order; a delay device 102 which delays a received signal; and a subtractor 112 which subtracts a result of the respreading from the delayed data. For each symbol, the largest likelihood is selected, and a replica is generated by using it. A desired performance is attained by performing one provisional decision and one demodulation. Therefore, computational complexity is reduced and realization is facilitated.

Abstract: Received data representing voice information is subjected to Viterbi decoding to correct an error in the received data. Thereby, the received data is decoded into second data. A path metric is calculated to determine the second data during the Viterbi decoding. A decision is made as to whether or not at least one error is present in the second data by referring to a cyclic redundancy check code in the second data. The second data is discarded when it is decided that at least one error is present in the second data. A decision is made as to whether or not the calculated path metric exceeds a threshold value. The second data is discarded when it is decided that the path metric exceeds the threshold value. The second data is converted into sound when it is decided that at least one error is not present in the second data and that the path metric does not exceed the threshold value.