Patents by Inventor Mitsuru Yoshikawa
Mitsuru Yoshikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8431465Abstract: Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a substrate having a trench that defines an active region, an isolation layer that buries the trench, a pro-oxidant region formed at an upper corner portion of the trench to enhance oxidation at the upper corner portion of the trench when a gate insulation layer is grown on the active region, and a gate conductive layer formed on the gate insulation layer.Type: GrantFiled: December 20, 2011Date of Patent: April 30, 2013Assignee: MagnaChip Semiconductor, Ltd.Inventors: Hiroshi Yamamoto, Mitsuru Yoshikawa
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Publication number: 20120104504Abstract: Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a substrate having a trench that defines an active region, an isolation layer that buries the trench, a pro-oxidant region formed at an upper corner portion of the trench to enhance oxidation at the upper corner portion of the trench when a gate insulation layer is grown on the active region, and a gate conductive layer formed on the gate insulation layer.Type: ApplicationFiled: December 20, 2011Publication date: May 3, 2012Inventors: Hiroshi Yamamoto, Mitsuru Yoshikawa
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Publication number: 20100052019Abstract: Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a substrate having a trench that defines an active region, an isolation layer that buries the trench, a pro-oxidant region formed at an upper corner portion of the trench to enhance oxidation at the upper corner portion of the trench when a gate insulation layer is grown on the active region, and a gate conductive layer formed on the gate insulation layer.Type: ApplicationFiled: July 29, 2009Publication date: March 4, 2010Inventors: Hiroshi YAMAMOTO, Mitsuru Yoshikawa
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Patent number: 7144780Abstract: The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset D2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.Type: GrantFiled: November 4, 2005Date of Patent: December 5, 2006Assignee: Texas Instruments IncorporatedInventors: Hirofumi Komori, Mitsuru Yoshikawa
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Patent number: 7138689Abstract: A semiconductor substrate that has a MOS transistor with a high breakdown voltage having double sidewall insulation films and can inhibit negative effects on the electric characteristics and method thereof.Type: GrantFiled: December 18, 2003Date of Patent: November 21, 2006Assignee: Texas Instruments IncorporatedInventors: Tsuyoshi Inoue, Hiroshi Yamamoto, Mitsuru Yoshikawa, Saiki Hotate
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Publication number: 20060057798Abstract: The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset D2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.Type: ApplicationFiled: November 4, 2005Publication date: March 16, 2006Inventors: Hirofumi Komori, Mitsuru Yoshikawa
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Publication number: 20050106827Abstract: The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset d2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.Type: ApplicationFiled: November 5, 2004Publication date: May 19, 2005Inventors: Hirofumi Komori, Mitsuru Yoshikawa
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Patent number: 6847080Abstract: The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset d2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.Type: GrantFiled: December 19, 2002Date of Patent: January 25, 2005Assignee: Texas Instruments IncorporatedInventors: Hirofumi Komori, Mitsuru Yoshikawa
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Publication number: 20040152244Abstract: A MOSFET semiconductor device and its fabrication method by which effects of parasitic transistors can be eliminated, subthreshold characteristic can be improved, and the threshold can be regulated easily.Type: ApplicationFiled: December 18, 2003Publication date: August 5, 2004Inventors: Hiroshi Yamamoto, Tsuyoshi Inoue, Mitsuru Yoshikawa, Saiki Hotate
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Publication number: 20040150066Abstract: A semiconductor substrate that has a MOS transistor with a high breakdown voltage having double sidewall insulation films and can inhibit negative effects on the electric characteristics and method thereof.Type: ApplicationFiled: December 18, 2003Publication date: August 5, 2004Inventors: Tsuyoshi Inoue, Hiroshi Yamamoto, Mitsuru Yoshikawa, Saiki Hotate
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Publication number: 20030124864Abstract: The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset d2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.Type: ApplicationFiled: December 19, 2002Publication date: July 3, 2003Inventors: Hirofumi Komori, Mitsuru Yoshikawa
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Patent number: 6134769Abstract: The rubber plug fitting apparatus includes a temporary receiver (4) disposed after the feeder (3); a rubber plug holder (5) pivotable 90 degrees by a first drive means (29); a transfer pin (7) for transferring the rubber plug (2) to the holder (5); a wire guide (11) disposed opposite the holder (5) when the latter is pivotated 90 degrees with the rubber plug held therein, which supports a wire (9); a second drive means (37) for moving the holder in a rubber plug fitting direction; and a third drive means (36) for moving the guide (11) in the same direction. A waterproofing rubber plug is reliably fitted over a wire with high positional accuracy.Type: GrantFiled: June 9, 1999Date of Patent: October 24, 2000Assignee: Yazaki CorporationInventors: Yukinori Takano, Mitsuru Yoshikawa, Akira Sugiyama
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Patent number: 5926947Abstract: The rubber plug fitting apparatus includes a temporary receiver (4) disposed after the feeder (3); a rubber plug holder (5) pivotable 90 degrees by a first drive means (29); a transfer pin (7) for transferring the rubber plug (2) to the holder (5); a wire guide (11) disposed opposite the holder (5) when the latter is pivotated 90 degrees with the rubber plug held therein, which supports a wire (9); a second drive means (37) for moving the holder in a rubber plug fitting direction; and a third drive means (36) for moving the guide (11) in the same direction. A waterproofing rubber plug is reliably fitted over a wire with high positional accuracy.Type: GrantFiled: February 27, 1997Date of Patent: July 27, 1999Assignee: Yazaki CorporationInventors: Yukinori Takano, Mitsuru Yoshikawa, Akira Sugiyama
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Patent number: 5921125Abstract: A method of controlling a terminal press attaching device by providing a elevating crimper for crimping terminals onto exposed conductors of the cables, setting an anvil opposite to the crimper, and elevating the drive means including a servo motor. More specifically, the crimp height for press attached terminals is monitored, a detected height and the predetermined set value are compared to control said drive means such that the detected height is made equal to the set value. Thus, the crimp height of the terminal to be attached (or the crimper height) is automatically and easily adjusted.Type: GrantFiled: June 10, 1997Date of Patent: July 13, 1999Assignee: Yazaki CorporationInventors: Toshihiro Inoue, Tatsuya Maeda, Mitsuru Yoshikawa, Chiaki Hatano, Yukinori Takano
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Patent number: 4552353Abstract: A paper feeding apparatus is provided with a paper feeding roller and a paper separating plate mounted on an end of a spring-biased swingable lever. Paper sheets are separated, one sheet from the other, at a gap between the paper feeding roller and the paper separating plate. A guiding means is provided in opposition to a swingable part of the lever, and a stopper is interposed in a space between the swingable part of the lever and the guiding means. The stopper is movably biased into mechanical engagement with the swingable part of the lever, thereby to prevent double-feed of paper sheets by maintaining a predetermined extent of the gap between the paper feeding roller and the paper separating plate.Type: GrantFiled: December 20, 1983Date of Patent: November 12, 1985Assignee: Duplo Seizo Kabushiki KaishaInventors: Kazunori Tanaka, Mitsuru Yoshikawa