Patents by Inventor Mitsuru Yoshikawa

Mitsuru Yoshikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8431465
    Abstract: Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a substrate having a trench that defines an active region, an isolation layer that buries the trench, a pro-oxidant region formed at an upper corner portion of the trench to enhance oxidation at the upper corner portion of the trench when a gate insulation layer is grown on the active region, and a gate conductive layer formed on the gate insulation layer.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: April 30, 2013
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Hiroshi Yamamoto, Mitsuru Yoshikawa
  • Publication number: 20120104504
    Abstract: Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a substrate having a trench that defines an active region, an isolation layer that buries the trench, a pro-oxidant region formed at an upper corner portion of the trench to enhance oxidation at the upper corner portion of the trench when a gate insulation layer is grown on the active region, and a gate conductive layer formed on the gate insulation layer.
    Type: Application
    Filed: December 20, 2011
    Publication date: May 3, 2012
    Inventors: Hiroshi Yamamoto, Mitsuru Yoshikawa
  • Publication number: 20100052019
    Abstract: Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a substrate having a trench that defines an active region, an isolation layer that buries the trench, a pro-oxidant region formed at an upper corner portion of the trench to enhance oxidation at the upper corner portion of the trench when a gate insulation layer is grown on the active region, and a gate conductive layer formed on the gate insulation layer.
    Type: Application
    Filed: July 29, 2009
    Publication date: March 4, 2010
    Inventors: Hiroshi YAMAMOTO, Mitsuru Yoshikawa
  • Patent number: 7144780
    Abstract: The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset D2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: December 5, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Hirofumi Komori, Mitsuru Yoshikawa
  • Patent number: 7138689
    Abstract: A semiconductor substrate that has a MOS transistor with a high breakdown voltage having double sidewall insulation films and can inhibit negative effects on the electric characteristics and method thereof.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: November 21, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Tsuyoshi Inoue, Hiroshi Yamamoto, Mitsuru Yoshikawa, Saiki Hotate
  • Publication number: 20060057798
    Abstract: The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset D2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.
    Type: Application
    Filed: November 4, 2005
    Publication date: March 16, 2006
    Inventors: Hirofumi Komori, Mitsuru Yoshikawa
  • Publication number: 20050106827
    Abstract: The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset d2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.
    Type: Application
    Filed: November 5, 2004
    Publication date: May 19, 2005
    Inventors: Hirofumi Komori, Mitsuru Yoshikawa
  • Patent number: 6847080
    Abstract: The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset d2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: January 25, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Hirofumi Komori, Mitsuru Yoshikawa
  • Publication number: 20040152244
    Abstract: A MOSFET semiconductor device and its fabrication method by which effects of parasitic transistors can be eliminated, subthreshold characteristic can be improved, and the threshold can be regulated easily.
    Type: Application
    Filed: December 18, 2003
    Publication date: August 5, 2004
    Inventors: Hiroshi Yamamoto, Tsuyoshi Inoue, Mitsuru Yoshikawa, Saiki Hotate
  • Publication number: 20040150066
    Abstract: A semiconductor substrate that has a MOS transistor with a high breakdown voltage having double sidewall insulation films and can inhibit negative effects on the electric characteristics and method thereof.
    Type: Application
    Filed: December 18, 2003
    Publication date: August 5, 2004
    Inventors: Tsuyoshi Inoue, Hiroshi Yamamoto, Mitsuru Yoshikawa, Saiki Hotate
  • Publication number: 20030124864
    Abstract: The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset d2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.
    Type: Application
    Filed: December 19, 2002
    Publication date: July 3, 2003
    Inventors: Hirofumi Komori, Mitsuru Yoshikawa
  • Patent number: 6134769
    Abstract: The rubber plug fitting apparatus includes a temporary receiver (4) disposed after the feeder (3); a rubber plug holder (5) pivotable 90 degrees by a first drive means (29); a transfer pin (7) for transferring the rubber plug (2) to the holder (5); a wire guide (11) disposed opposite the holder (5) when the latter is pivotated 90 degrees with the rubber plug held therein, which supports a wire (9); a second drive means (37) for moving the holder in a rubber plug fitting direction; and a third drive means (36) for moving the guide (11) in the same direction. A waterproofing rubber plug is reliably fitted over a wire with high positional accuracy.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: October 24, 2000
    Assignee: Yazaki Corporation
    Inventors: Yukinori Takano, Mitsuru Yoshikawa, Akira Sugiyama
  • Patent number: 5926947
    Abstract: The rubber plug fitting apparatus includes a temporary receiver (4) disposed after the feeder (3); a rubber plug holder (5) pivotable 90 degrees by a first drive means (29); a transfer pin (7) for transferring the rubber plug (2) to the holder (5); a wire guide (11) disposed opposite the holder (5) when the latter is pivotated 90 degrees with the rubber plug held therein, which supports a wire (9); a second drive means (37) for moving the holder in a rubber plug fitting direction; and a third drive means (36) for moving the guide (11) in the same direction. A waterproofing rubber plug is reliably fitted over a wire with high positional accuracy.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: July 27, 1999
    Assignee: Yazaki Corporation
    Inventors: Yukinori Takano, Mitsuru Yoshikawa, Akira Sugiyama
  • Patent number: 5921125
    Abstract: A method of controlling a terminal press attaching device by providing a elevating crimper for crimping terminals onto exposed conductors of the cables, setting an anvil opposite to the crimper, and elevating the drive means including a servo motor. More specifically, the crimp height for press attached terminals is monitored, a detected height and the predetermined set value are compared to control said drive means such that the detected height is made equal to the set value. Thus, the crimp height of the terminal to be attached (or the crimper height) is automatically and easily adjusted.
    Type: Grant
    Filed: June 10, 1997
    Date of Patent: July 13, 1999
    Assignee: Yazaki Corporation
    Inventors: Toshihiro Inoue, Tatsuya Maeda, Mitsuru Yoshikawa, Chiaki Hatano, Yukinori Takano
  • Patent number: 4552353
    Abstract: A paper feeding apparatus is provided with a paper feeding roller and a paper separating plate mounted on an end of a spring-biased swingable lever. Paper sheets are separated, one sheet from the other, at a gap between the paper feeding roller and the paper separating plate. A guiding means is provided in opposition to a swingable part of the lever, and a stopper is interposed in a space between the swingable part of the lever and the guiding means. The stopper is movably biased into mechanical engagement with the swingable part of the lever, thereby to prevent double-feed of paper sheets by maintaining a predetermined extent of the gap between the paper feeding roller and the paper separating plate.
    Type: Grant
    Filed: December 20, 1983
    Date of Patent: November 12, 1985
    Assignee: Duplo Seizo Kabushiki Kaisha
    Inventors: Kazunori Tanaka, Mitsuru Yoshikawa