Abstract: An evaluation device according to the present disclosure groups unit data in a unit data collection into two or more groups each including at least one of a plurality of data items, calculates, as a per-group unit space, a unit space in each of two or more per-group unit data collections which are unit data collections obtained by grouping the unit data into the two or more groups, calculates, using the per-group unit space calculated, a first Mahalanobis distance of a corresponding per-group unit data collection and a second Mahalanobis distance of a signal data collection in a corresponding data item, calculates a first linear combination of a plurality of first Mahalanobis distances calculated and a second linear combination of a plurality of second Mahalanobis distances calculated, compares the first and second linear combinations calculated, and outputs the comparison result as a first comparison result.

Abstract: In a semiconductor integrated circuit device, arrangement relationship of power source area I/O pads differs between a peripheral portion and a center portion of a gate region of a chip. That is, in two columns and two rows of the peripheral portion of the gate region, VDD area I/O pads connected to a high-voltage power source VDD and GND area I/O pads connected to a ground power source GND are alternately aligned and arranged both in a row direction and in a column direction. Moreover, in the center portion of the gate region, the same VDD area I/O pads or the same GND area I/O pads are successively aligned in the row direction, and the VDD area I/O pads and the GND area I/O pads are alternately aligned and arranged in the column direction.

Abstract: In a semiconductor integrated circuit device, arrangement relationship of power source area I/O pads differs between a peripheral portion and a center portion of a gate region of a chip. That is, in two columns and two rows of the peripheral portion of the gate region, VDD area I/O pads connected to a high-voltage power source VDD and GND area I/O pads connected to a ground power source GND are alternately aligned and arranged both in a row direction and in a column direction. Moreover, in the center portion of the gate region, the same VDD area I/O pads or the same GND area I/O pads are successively aligned in the row direction, and the VDD area I/O pads and the GND area I/O pads are alternately aligned and arranged in the column direction.

Abstract: The object of the present invention is to provide a semiconductor integrated circuit which enables reduction in clock skew between cell blocks, while having plural cell blocks in which standard cells with different cell heights are arranged. The semiconductor integrated circuit of the present invention includes a first standard cell and a second standard cell having a cell height different from a cell height of the first standard cell, and in a P-well region of the first standard cell, the following are arranged: a pair of N-type diffusion regions; and a P-type diffusion region for supplying first substrate power to the first standard cell, and in a P-well region of the second standard cell, the following are arranged: a pair of N-type diffusion regions; and a P-type diffusion region for supplying second substrate power to the second standard cell.

Abstract: To prevent the potential inversion of a dynamic node attributed to the fact that any wiring line among standard cells as is made of a wiring layer at the same level as that of the dynamic node within a standard cell is laid in adjacency to the dynamic node. In adjacency to a dynamic node 101 within a standard cell, shield wiring lines 102a and 102b which are made of wiring layers at the same level as that of the dynamic node are laid so as to prevent any wiring line among standard cells from passing in adjacency to the dynamic node. The shield wiring lines can be replaced with a shield region or a wiring inhibition region.

Abstract: A semiconductor integrated circuit comprises: a first standard cell which includes a first logic circuit and a first switch for controlling current supply to the first logic circuit; and a second standard cell which includes a second logic circuit and a second switch for controlling current supply to the second logic circuit. The first switch is shared with the second standard cell as the second switch.

Abstract: To prevent the potential inversion of a dynamic node attributed to the fact that any wiring line among standard cells as is made of a wiring layer at the same level as that of the dynamic node within a standard cell is laid in adjacency to the dynamic node. In adjacency to a dynamic node 101 within a standard cell, shield wiring lines 102a and 102b which are made of wiring layers at the same level as that of the dynamic node are laid so as to prevent any wiring line among standard cells from passing in adjacency to the dynamic node. The shield wiring lines can be replaced with a shield region or a wiring inhibition region.