Patents by Inventor Mitsutaka Izawa

Mitsutaka Izawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8304340
    Abstract: A semiconductor device manufacturing method including: forming a first interlayer insulating film on a semiconductor substrate; forming a first hole in the first interlayer insulating film; forming a barrier film inside the first hole; filling a conductive material in the first hole to form a first plug; forming a second interlayer insulating film on the first interlayer insulating film; forming a second hole reaching the first plug in the second interlayer insulating film; selectively etching an upper end of the barrier film inside the second hole; and forming a second plug for connection to the first plug inside the second hole.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: November 6, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Mitsutaka Izawa
  • Publication number: 20110021018
    Abstract: A semiconductor device manufacturing method including: forming a first interlayer insulating film on a semiconductor substrate; forming a first hole in the first interlayer insulating film; forming a barrier film inside the first hole; filling a conductive material in the first hole to form a first plug; forming a second interlayer insulating film on the first interlayer insulating film; forming a second hole reaching the first plug in the second interlayer insulating film; selectively etching an upper end of the barrier film inside the second hole; and forming a second plug for connection to the first plug inside the second hole.
    Type: Application
    Filed: June 18, 2010
    Publication date: January 27, 2011
    Applicant: Elpida Memory, Inc.
    Inventor: Mitsutaka Izawa
  • Patent number: 7656693
    Abstract: In a memory cell area of a semiconductor device, first, second, and third inter-layer insulating films respectively cover a cell transistor, a bit wiring line, and a capacitor which are connected to each other. In an adjacent peripheral circuit area, a peripheral-circuit transistor is covered with the first inter-layer insulating film, a first-layer wiring line connected to the peripheral-circuit transistor is provided on the first inter-layer insulating film and covered with the second inter-layer insulating film, and a second-layer wiring line is provided on the third inter-layer insulating film. In the memory cell area, a landing pad is provided on the second inter-layer insulating film and between the capacitor and a contact plug for connecting the capacitor to the cell transistor. An assist wiring line connected to the first-layer wiring line is provided on the main surface of the second inter-layer insulating film, on which the landing pad is provided.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: February 2, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Yoshitaka Nakamura, Mitsutaka Izawa
  • Publication number: 20080239815
    Abstract: In a memory cell area of a semiconductor device, first, second, and third inter-layer insulating films respectively cover a cell transistor, a bit wiring line, and a capacitor which are connected to each other. In an adjacent peripheral circuit area, a peripheral-circuit transistor is covered with the first inter-layer insulating film, a first-layer wiring line connected to the peripheral-circuit transistor is provided on the first inter-layer insulating film and covered with the second inter-layer insulating film, and a second-layer wiring line is provided on the third inter-layer insulating film. In the memory cell area, a landing pad is provided on the second inter-layer insulating film and between the capacitor and a contact plug for connecting the capacitor to the cell transistor. An assist wiring line connected to the first-layer wiring line is provided on the main surface of the second inter-layer insulating film, on which the landing pad is provided.
    Type: Application
    Filed: March 13, 2008
    Publication date: October 2, 2008
    Inventors: Yoshitaka NAKAMURA, Mitsutaka IZAWA
  • Publication number: 20010044214
    Abstract: In a method for dry-etching a multilayer film which contains a titanium nitride film and which is formed on a silicon dioxide layer, after the multilayer film is etched by using a Cl2/BCl3/CHF3 gas while using a resist as a mask, but before the resist is ashed for removal of the resist, an overetching is carried out using a gas containing at least 50% of SF6, thereby to elevate removability of the resist by the ashing.
    Type: Application
    Filed: April 10, 2000
    Publication date: November 22, 2001
    Inventor: Mitsutaka Izawa
  • Patent number: 6214725
    Abstract: An etching method can restrict side etching (corrosion) of an AlCu film as an upper layer upon etching of a TiN film as a lower layer. The etching method is characterized by, upon etching of a stacked film of AlCu film/TiN film with taking an oxide film as a mask, as a gas for performing etching of TiN film on a lower layer, a compound gas containing a chlorine atom is used, and using a mixture gas of the etching gas and an additive gas and not using a Cl2, a corrosion resistance of AlCu film against the etching gas can be improved.
    Type: Grant
    Filed: December 16, 1998
    Date of Patent: April 10, 2001
    Assignee: NEC Corporation
    Inventor: Mitsutaka Izawa