Patents by Inventor Mitsutaka Matsumoto

Mitsutaka Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11965785
    Abstract: Provided is a pressure-sensitive element having more sufficient expandability, a relatively wide measurement range of pressure force, and a relatively simple structure, and an electronic device using the pressure-sensitive element. The pressure-sensitive element includes a plurality of first electrodes being elongated in first direction, arranged in a first plane, and including a conductive elastic body, a plurality of second electrodes being elongated in second direction intersecting the first direction, arranged in a second plane facing the first plane, and including a conductor wire, and a plurality of dielectrics covering a surface of the plurality of second electrodes. The plurality of second electrodes have bent parts K arranged periodically, and capacitance at intersections of the plurality of first electrodes and the plurality of second electrodes changes in accordance with pressure force applied between the plurality of first electrodes and the plurality of second electrodes.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: April 23, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yuta Moriura, Yui Sawada, Shinobu Masuda, Hironobu Ukitsu, Takashi Matsumoto, Mitsutaka Matsumoto
  • Patent number: 11740141
    Abstract: Provided is a pressure-sensitive element having a relatively wide measurement range of a pressing force and a relatively simple structure while having more sufficient stretchability. A pressure-sensitive element includes a base material, a plurality of conductor wires, a plurality of dielectrics, and a filamentous member. The base material includes an elastic conductor having elasticity and conductivity. Further, the base material has a sheet shape. The plurality of conductor wires are arranged in parallel so as to individually intersect with the elastic conductor in plan view. Further, each of the plurality of conductor wires has a plurality of inflection parts. The plurality of dielectrics are arranged between the elastic conductor and the plurality of conductor wires. The filamentous member elongates so as to intersect with the plurality of conductor wires in plan view. Further, the filamentous member sews the plurality of conductor wires to the base material.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: August 29, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Susumu Uragami, Hiroyuki Furuya, Yuta Moriura, Takashi Matsumoto, Hironobu Ukitsu, Shinobu Masuda, Mitsutaka Matsumoto, Yui Sawada
  • Publication number: 20210318188
    Abstract: Provided is a pressure-sensitive element having a relatively wide measurement range of a pressing force and a relatively simple structure while having more sufficient stretchability. A pressure-sensitive element includes a base material, a plurality of conductor wires, a plurality of dielectrics, and a filamentous member. The base material includes an elastic conductor having elasticity and conductivity. Further, the base material has a sheet shape. The plurality of conductor wires are arranged in parallel so as to individually intersect with the elastic conductor in plan view. Further, each of the plurality of conductor wires has a plurality of inflection parts. The plurality of dielectrics are arranged between the elastic conductor and the plurality of conductor wires. The filamentous member elongates so as to intersect with the plurality of conductor wires in plan view. Further, the filamentous member sews the plurality of conductor wires to the base material.
    Type: Application
    Filed: June 22, 2021
    Publication date: October 14, 2021
    Inventors: SUSUMU URAGAMI, HIROYUKI FURUYA, YUTA MORIURA, TAKASHI MATSUMOTO, HIRONOBU UKITSU, SHINOBU MASUDA, MITSUTAKA MATSUMOTO, YUI SAWADA
  • Publication number: 20210223119
    Abstract: Provided is a pressure-sensitive element having more sufficient expandability, a relatively wide measurement range of pressure force, and a relatively simple structure, and an electronic device using the pressure-sensitive element. The pressure-sensitive element includes a plurality of first electrodes being elongated in first direction, arranged in a first plane, and including a conductive elastic body, a plurality of second electrodes being elongated in second direction intersecting the first direction, arranged in a second plane facing the first plane, and including a conductor wire, and a plurality of dielectrics covering a surface of the plurality of second electrodes. The plurality of second electrodes have bent parts K arranged periodically, and capacitance at intersections of the plurality of first electrodes and the plurality of second electrodes changes in accordance with pressure force applied between the plurality of first electrodes and the plurality of second electrodes.
    Type: Application
    Filed: April 2, 2021
    Publication date: July 22, 2021
    Inventors: YUTA MORIURA, YUI SAWADA, SHINOBU MASUDA, HIRONOBU UKITSU, TAKASHI MATSUMOTO, MITSUTAKA MATSUMOTO
  • Patent number: 10535779
    Abstract: A thin film transistor includes a gate electrode. The thin film transistor further includes an oxide semiconductor layer which includes at least indium and is usable as a channel layer, wherein a region of the oxide semiconductor layer closest to the gate electrode includes fluorine. The thin film transistor further includes a gate insulating layer between the gate electrode and the oxide semiconductor layer. The thin film transistor further includes a fluorine-including layer which includes fluorine and is between the gate electrode and the gate insulating layer.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: January 14, 2020
    Assignee: JOLED INC.
    Inventor: Mitsutaka Matsumoto
  • Patent number: 10138377
    Abstract: A lignin derivative that is extracted from biomass and is used for rubber reinforcement or for use in a molding material is provided. Such a lignin derivative has a number average molecular weight of 300 to 2,000, and contains a component that is soluble in a polar organic solvent, in an amount of 80% by mass or more. When such a lignin derivative is incorporated, a lignin resin composition, a rubber composition, or a molding material, all of which have excellent low hysteresis loss characteristics, elastic modulus, or tensile properties, can be obtained. Furthermore, when a component that is thermofusible is used as the soluble component, a lignin resin composition, a rubber composition, or a molding material, all of which have superior aforementioned characteristics, can be obtained.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: November 27, 2018
    Assignee: SUMITOMO BAKELITE CO., LTD.
    Inventors: Taketoshi Murai, Hiroshige Nakagawa, Mitsutaka Matsumoto
  • Patent number: 10059793
    Abstract: Provided is a lignin resin composition including a lignin derivative having a weight-average molecular weight of 500 or more and 4000 or less and a novolac-type phenolic resin having a weight-average molecular weight of 1000 or more and 3000 or less, in which the content of the lignin derivative is not higher than the content of the novolac-type phenolic resin. In particular, the cured product (molded product) of a lignin resin composition obtained by melt-mixing such a lignin resin composition, adding hexamethylenetetramine thereto and then heating the resulting mixture has a high bending strength. Such a lignin resin composition is utilizable as a thermosetting resin substituting a phenolic resin.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: August 28, 2018
    Assignee: SUMITOMO BAKELITE CO., LTD.
    Inventors: Hiroshige Nakagawa, Mitsutaka Matsumoto, Taketoshi Murai
  • Patent number: 10008611
    Abstract: A thin film transistor includes: a substrate; an undercoat layer disposed on the substrate; an oxide semiconductor layer formed above the undercoat layer and including at least indium; a gate insulating layer located opposite the undercoat layer with the oxide semiconductor layer being between the gate insulating layer and the undercoat layer; a gate electrode located opposite the oxide semiconductor layer with the gate insulating layer being between the gate electrode and the oxide semiconductor layer; and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, wherein fluorine is included in a region which is an internal region in the oxide semiconductor layer and is close to the undercoat layer.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: June 26, 2018
    Assignee: JOLED INC.
    Inventors: Mitsutaka Matsumoto, Arinobu Kanegae
  • Publication number: 20180158954
    Abstract: A thin film transistor includes a gate electrode. The thin film transistor further includes an oxide semiconductor layer which includes at least indium and is usable as a channel layer, wherein a region of the oxide semiconductor layer closest to the gate electrode includes fluorine. The thin film transistor further includes a gate insulating layer between the gate electrode and the oxide semiconductor layer. The thin film transistor further includes a fluorine-including layer which includes fluorine and is between the gate electrode and the gate insulating layer.
    Type: Application
    Filed: January 16, 2018
    Publication date: June 7, 2018
    Inventor: Mitsutaka MATSUMOTO
  • Patent number: 9871097
    Abstract: A thin film transistor includes: a gate electrode; a gate insulating layer above the gate electrode; an oxide semiconductor layer disposed above the gate insulating layer; and a source electrode and a drain electrode disposed above the oxide semiconductor layer and electrically connected to the oxide semiconductor layer, wherein metallic elements included in the oxide semiconductor layer include at least indium (In), fluorine is included in a region which is an internal region in the oxide semiconductor layer and is close to the gate insulating layer, and a fluorine concentration of the region close to the gate insulating layer in the oxide semiconductor layer is higher than a fluorine of a contact region for the source electrode or the drain electrode in the oxide semiconductor layer.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: January 16, 2018
    Assignee: JOLED INC.
    Inventor: Mitsutaka Matsumoto
  • Publication number: 20170342188
    Abstract: Provided is a lignin resin composition including a lignin derivative having a weight-average molecular weight of 500 or more and 4000 or less and a novolac-type phenolic resin having a weight-average molecular weight of 1000 or more and 3000 or less, in which the content of the lignin derivative is not higher than the content of the novolac-type phenolic resin. In particular, the cured product (molded product) of a lignin resin composition obtained by melt-mixing such a lignin resin composition, adding hexamethylenetetramine thereto and then heating the resulting mixture has a high bending strength. Such a lignin resin composition is utilizable as a thermosetting resin substituting a phenolic resin.
    Type: Application
    Filed: November 18, 2015
    Publication date: November 30, 2017
    Applicant: SUMITOMO BAKELITE CO., LTD.
    Inventors: Hiroshige Nakagawa, Mitsutaka Matsumoto, Taketoshi Murai
  • Publication number: 20170253740
    Abstract: A lignin derivative that is extracted from biomass and is used for rubber reinforcement or for use in a molding material is provided. Such a lignin derivative has a number average molecular weight of 300 to 2,000, and contains a component that is soluble in a polar organic solvent, in an amount of 80% by mass or more. When such a lignin derivative is incorporated, a lignin resin composition, a rubber composition, or a molding material, all of which have excellent low hysteresis loss characteristics, elastic modulus, or tensile properties, can be obtained. Furthermore, when a component that is thermofusible is used as the soluble component, a lignin resin composition, a rubber composition, or a molding material, all of which have superior aforementioned characteristics, can be obtained.
    Type: Application
    Filed: August 31, 2015
    Publication date: September 7, 2017
    Applicant: SUMITOMO BAKELITE CO., LTD.
    Inventors: Taketoshi Murai, Hiroshige Nakagawa, Mitsutaka Matsumoto
  • Publication number: 20170162713
    Abstract: A thin film transistor includes: a gate electrode; a source electrode and a drain electrode; an oxide semiconductor layer used as a channel layer; and a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer, wherein metallic elements included in the oxide semiconductor layer include at least indium (In), and fluorine (F) is included in a region which is an internal region in the oxide semiconductor layer and is close to the gate insulating layer.
    Type: Application
    Filed: June 17, 2015
    Publication date: June 8, 2017
    Inventor: Mitsutaka MATSUMOTO
  • Publication number: 20170148924
    Abstract: A thin film transistor includes: a gate electrode; a gate insulating layer above the gate electrode; an oxide semiconductor layer disposed above the gate insulating layer; and a source electrode and a drain electrode disposed above the oxide semiconductor layer and electrically connected to the oxide semiconductor layer, wherein metallic elements included in the oxide semiconductor layer include at least indium (In), fluorine is included in a region which is an internal region in the oxide semiconductor layer and is close to the gate insulating layer, and a fluorine concentration of the region close to the gate insulating layer in the oxide semiconductor layer is higher than a fluorine of a contact region for the source electrode or the drain electrode in the oxide semiconductor layer.
    Type: Application
    Filed: June 17, 2015
    Publication date: May 25, 2017
    Inventor: Mitsutaka MATSUMOTO
  • Publication number: 20170141231
    Abstract: A thin film transistor includes: a substrate; an undercoat layer disposed on the substrate; an oxide semiconductor layer formed above the undercoat layer and including at least indium; a gate insulating layer located opposite the undercoat layer with the oxide semiconductor layer being between the gate insulating layer and the undercoat layer; a gate electrode located opposite the oxide semiconductor layer with the gate insulating layer being between the gate electrode and the oxide semiconductor layer; and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, wherein fluorine is included in a region which is an internal region in the oxide semiconductor layer and is close to the undercoat layer.
    Type: Application
    Filed: June 24, 2015
    Publication date: May 18, 2017
    Applicant: JOLED INC.
    Inventors: Mitsutaka MATSUMOTO, Arinobu KANEGAE
  • Patent number: 9125822
    Abstract: A main object of the invention is to provide a particle for medical use which has an excellent capability of fixing a target biologically active substance and has such chemical and physical stability that the particle is less dissolved or deteriorated in a washing step. The present invention has solved the above problem with a particle for medical use having a layer containing a polymer compound formed on a surface of a core particle, wherein the polymer compound is a polymer comprising at least repeating units derived from an ethylenically unsaturated polymerizable monomer (a) having a functional group for fixing a biologically active substance, wherein the polymer has a reactive functional group on at least one terminal side thereof.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: September 8, 2015
    Assignee: SUMITOMO BAKELITE COMPANY, LTD.
    Inventors: Takayuki Matsumoto, Mitsutaka Matsumoto, Yoshiaki Fukunishi, Kazuya Kitagawa, Yuzo Hamaguchi
  • Patent number: 9012914
    Abstract: A method for manufacturing a thin-film transistor includes: preparing a substrate; forming a gate electrode above the substrate; forming a gate insulating layer above the gate electrode; forming a semiconductor film above the gate insulating layer; forming, above the semiconductor film, a protective layer comprising an organic material; forming a source electrode and a drain electrode which are opposed to each other and each of which has at least a portion located above the protective layer; forming a semiconductor layer patterned, by performing dry etching on the semiconductor film; and performing, in a hydrogen atmosphere, plasma treatment on an altered layer which (i) is a surface layer of the protective layer exposed from the source electrode and the drain electrode and altered by the dry etching, and (ii) has at least a portion contacting a surface of the semiconductor layer.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: April 21, 2015
    Assignee: Panasonic Corporation
    Inventors: Yuji Kishida, Kenichirou Nishida, Mitsutaka Matsumoto
  • Publication number: 20140124783
    Abstract: A method for manufacturing a thin-film transistor includes: preparing a substrate; forming a gate electrode above the substrate; forming a gate insulating layer above the gate electrode; forming a semiconductor film above the gate insulating layer; forming, above the semiconductor film, a protective layer comprising an organic material; forming a source electrode and a drain electrode which are opposed to each other and each of which has at least a portion located above the protective layer; forming a semiconductor layer patterned, by performing dry etching on the semiconductor film; and performing, in a hydrogen atmosphere, plasma treatment on an altered layer which (i) is a surface layer of the protective layer exposed from the source electrode and the drain electrode and altered by the dry etching, and (ii) has at least a portion contacting a surface of the semiconductor layer.
    Type: Application
    Filed: May 29, 2013
    Publication date: May 8, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Yuji Kishida, Kenichirou Nishida, Mitsutaka Matsumoto
  • Patent number: 8530900
    Abstract: Preparing a substrate; forming a plurality of gate electrodes above the substrate; forming a gate insulating layer above the gate electrodes; forming an amorphous silicon layer above the gate insulating layer; forming crystalline silicon layer regions by irradiating the amorphous silicon layer in regions above the gate electrodes with a laser beam having a wavelength from 473 nm to 561 nm so as to crystallize the amorphous silicon layer in the regions above the gate electrodes, and forming an amorphous silicon layer region in a region other than the regions above the gate electrodes; and forming source electrodes and drain electrodes above the crystalline silicon layer regions are included, and a thickness of the gate insulating layer and a thickness of the amorphous silicon layer satisfy predetermined expressions.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: September 10, 2013
    Assignee: Panasonic Corporation
    Inventors: Mitsutaka Matsumoto, Yuta Sugawara
  • Publication number: 20130134431
    Abstract: Preparing a substrate; forming a plurality of gate electrodes above the substrate; forming a gate insulating layer above the gate electrodes; forming an amorphous silicon layer above the gate insulating layer; forming crystalline silicon layer regions by irradiating the amorphous silicon layer in regions above the gate electrodes with a laser beam having a wavelength from 473 nm to 561 nm so as to crystallize the amorphous silicon layer in the regions above the gate electrodes, and forming an amorphous silicon layer region in a region other than the regions above the gate electrodes; and forming source electrodes and drain electrodes above the crystalline silicon layer regions are included, and a thickness of the gate insulating layer and a thickness of the amorphous silicon layer satisfy predetermined expressions.
    Type: Application
    Filed: June 13, 2012
    Publication date: May 30, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Mitsutaka MATSUMOTO, Yuta SUGAWARA