Patents by Inventor Mitsuteru Iijima
Mitsuteru Iijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9006793Abstract: A stacking structure in which a stacked body (21) including a first conductive layer (13), a semiconductor layer (17), and a second conductive layer (18) and an interlayer insulating film (16) are alternately stacked in parallel to a substrate, a plurality of columnar electrodes (12) arranged so as to penetrated through the stacking structure in a stacking direction, a variable resistance layer (14) which is disposed between the columnar electrode (12) and the first conductive layer (13) and which has a resistance value that reversibly changes according to an application of an electric signal are included. The variable resistance layer (14) is formed by oxidizing part of the first conductive layer (13). The variable resistance layer (14) and an insulating film for electrically separating the semiconductor layer (17) and the second conductive layer (18) from the columnar electrode (12) are simultaneously formed in a single oxidation process.Type: GrantFiled: June 29, 2011Date of Patent: April 14, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Zhiqiang Wei, Takeshi Takagi, Mitsuteru Iijima
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Patent number: 8710484Abstract: A manufacturing method for manufacturing, with a simple process, a non-volatile memory apparatus having a stable memory performance includes: (a) forming a stacking-structure body above a substrate by alternately stacking conductive layers comprising a transition metal and interlayer insulating films comprising an insulating material; (b) forming a contact hole penetrating through the stacking-structure body to expose part of each of the conductive layers; (c) forming variable resistance layers by oxidizing the part of each of the conductive layers, the part being exposed in the contact hole, and each of the variable resistance layers having a resistance value that reversibly changes according to an application of an electric signal; and (d) forming a pillar electrode in the contact hole by embedding a conductive material in the contact hole, the pillar electrode being connected to each of the variable resistance layers.Type: GrantFiled: February 23, 2011Date of Patent: April 29, 2014Assignee: Panasonic CorporationInventors: Zhiqiang Wei, Takeshi Takagi, Mitsuteru Iijima
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Patent number: 8675393Abstract: Provided is a method for driving a non-volatile memory element in which a variable resistance element including a first electrode, a second electrode, and a variable resistance layer capable of reversibly changing between a high resistance state and a low resistance state with application of electrical signals having different polarities is connected in series with a current steering element having bidirectional rectifying characteristics with respect to an applied voltage. After the non-volatile memory element is manufactured, the resistance value of the variable resistance layer is reduced from a resistance value in the initial resistance state higher than that in the high resistance state by applying, to the non-volatile memory element, a voltage pulse having the polarity identical to that of the voltage pulse for changing the variable resistance layer from the low resistance state to the high resistance state in the normal operations.Type: GrantFiled: March 18, 2011Date of Patent: March 18, 2014Assignee: Panasonic CorporationInventors: Koji Katayama, Takeshi Takagi, Mitsuteru Iijima
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Patent number: 8599602Abstract: Programming a variable resistance element includes: a writing step of applying a writing voltage pulse to transition metal oxide comprising two stacked metal oxide layers to decrease resistance of the metal oxide, each metal oxide layer having different oxygen deficiency; and an erasing step of applying an erasing voltage pulse, of different polarity than the writing pulse, to the metal oxide to increase resistance of the metal oxide. |Vw1|>|Vw2|. Vw1 represents writing voltage for first to N-th steps. Vw2 represents writing voltage for (N+1)-th and subsequent steps, where N?1, |Ve1|>|Ve2|. Ve1 represents erasing voltage for first to M-th steps. Ve2 represents erasing voltage for M+1-th and subsequent steps. tw1<te1. tw1 represents writing pulse width for first to N-th steps. te1 represents erasing pulse width for first to M-th steps. M?1. The (N+1)-th writing step follows the M-th erasing step.Type: GrantFiled: February 20, 2013Date of Patent: December 3, 2013Assignee: Panasonic CorporationInventors: Mitsuteru Iijima, Takeshi Takagi
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Patent number: 8565004Abstract: A method for programming a nonvolatile memory device according to the present invention includes a step of detecting an excessively low resistance cell from among a plurality of memory cells (11) (S101); a step of changing the resistance value of a load resistor (121) to a second resistance value smaller than a first resistance value (S103); and a step of causing, by applying a voltage pulse to a series circuit including the excessively low resistance cell and the load resistor (121) having the second resistance value, a variable resistance element (105) included in the excessively low resistance cell to shift to a second high resistance state having a resistance value greater than that of the first low resistance state (S104).Type: GrantFiled: June 28, 2011Date of Patent: October 22, 2013Assignee: Panasonic CorporationInventors: Mitsuteru Iijima, Takeshi Takagi, Koji Katayama
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Patent number: 8432721Abstract: Programming a variable resistance element includes: a writing step of applying a writing voltage pulse to transition metal oxide comprising two stacked metal oxide layers to decrease resistance of the metal oxide, each metal oxide layer having different oxygen deficiency; and an erasing step of applying an erasing voltage pulse, of different polarity than the writing pulse, to the metal oxide to increase resistance of the metal oxide. |Vw1|>|Vw2|, Vw1 representing voltage of the writing pulse for first to N-th writing steps, and Vw2 representing voltage of the writing pulse for (N+1)-th and subsequent writing steps, N being at least equal to 1, te1>te2, te1 representing pulse width of the erasing pulse for first to M-th erasing steps, and te2 representing pulse width of the erasing pulse for (M+1)-th and subsequent erasing steps. M>1. The (N+1)-th writing step follows the M-th erasing step.Type: GrantFiled: February 1, 2011Date of Patent: April 30, 2013Assignee: Panasonic CorporationInventors: Mitsuteru Iijima, Takeshi Takagi
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Patent number: 8422268Abstract: A memory element (3) arranged in matrix in a memory device and including a resistance variable element (1) which switches its electrical resistance value in response to a positive or negative electrical pulse applied thereto and retains the switched electrical resistance value; and a current control element (2) for controlling a current flowing when the electrical pulse is applied to the resistance variable element (1); wherein the current control element (2) includes a first electrode; a second electrode; and a current control layer sandwiched between the first electrode and the second electrode; and wherein the current control layer comprises SiNx, and at least one of the first electrode and the second electrode comprises ?-tungsten.Type: GrantFiled: May 1, 2009Date of Patent: April 16, 2013Assignee: Panasonic CorporationInventors: Koji Arita, Takumi Mikawa, Mitsuteru Iijima, Takashi Okada
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Patent number: 8355274Abstract: A current steering element which can prevent occurrence of write disturb even when electric pulses having different polarities are applied and can cause large current to flow through a variable resistance element, and with which data can be written without problem. In a storage element (3) including: a variable resistance element (1) whose electric resistance value changes in response to application of electric pulses having a positive polarity and a negative polarity and which maintains the changed electric resistance value; and the current steering element (2) that steers current flowing through the variable resistance element (1) when the electric pulses are applied, the current steering element (2) includes: a first electrode (32); a second electrode (31); and a current steering layer (33) interposed between the first electrode (32) and the second electrode (31). When the current steering layer (33) includes SiNx (0<x?0.Type: GrantFiled: September 17, 2009Date of Patent: January 15, 2013Assignee: Panasonic CorporationInventors: Koji Arita, Takumi Mikawa, Mitsuteru IIjima, Kenji Tominaga
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Publication number: 20130010530Abstract: Provided is a method for driving a non-volatile memory element in which a variable resistance element including a first electrode, a second electrode, and a variable resistance layer capable of reversibly changing between a high resistance state and a low resistance state with application of electrical signals having different polarities is connected in series with a current steering element having bidirectional rectifying characteristics with respect to an applied voltage. After the non-volatile memory element is manufactured, the resistance value of the variable resistance layer is reduced from a resistance value in the initial resistance state higher than that in the high resistance state by applying, to the non-volatile memory element, a voltage pulse having the polarity identical to that of the voltage pulse for changing the variable resistance layer from the low resistance state to the high resistance state in the normal operations.Type: ApplicationFiled: March 18, 2011Publication date: January 10, 2013Inventors: Koji Katayama, Takeshi Takagi, Mitsuteru Iijima
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Patent number: 8339835Abstract: A nonvolatile memory element includes a current controlling element having a non-linear current-voltage characteristic, a resistance variable element which changes reversibly between a low-resistance state and a high-resistance state in which a resistance value of the resistance variable element is higher than a resistance value of the resistance variable element in the low-resistance state, in response to voltage pulses applied, and a fuse. The current controlling element, the resistance variable element and the fuse are connected in series, and the fuse is configured to be blown when the current controlling element is substantially short-circuited.Type: GrantFiled: April 22, 2010Date of Patent: December 25, 2012Assignee: Panasonic CorporationInventors: Zhiqiang Wei, Takeshi Takagi, Mitsuteru Iijima
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Publication number: 20120319072Abstract: A manufacturing method for manufacturing, with a simple process, a non-volatile memory apparatus having a stable memory performance includes: (a) forming a stacking-structure body above a substrate by alternately stacking conductive layers comprising a transition metal and interlayer insulating films comprising an insulating material; (b) forming a contact hole penetrating through the stacking-structure body to expose part of each of the conductive layers; (c) forming variable resistance layers by oxidizing the part of each of the conductive layers, the part being exposed in the contact hole, and each of the variable resistance layers having a resistance value that reversibly changes according to an application of an electric signal; and (d) forming a pillar electrode in the contact hole by embedding a conductive material in the contact hole, the pillar electrode being connected to each of the variable resistance layers.Type: ApplicationFiled: February 23, 2011Publication date: December 20, 2012Inventors: Zhiqiang Wei, Takeshi Takagi, Mitsuteru Iijima
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Patent number: 8320159Abstract: Each of memory cells (MC) includes one transistor and one resistance variable element. The transistor includes a first main terminal, a second main terminal and a control terminal. The resistance variable element includes a first electrode, a second electrode and a resistance variable layer provided between the first electrode and the second electrode. A first main terminal of one of two adjacent memory cells is connected to a second main terminal of the other memory cell, to form a series path (SP) sequentially connecting main terminals of the plurality of memory cells in series.Type: GrantFiled: March 15, 2010Date of Patent: November 27, 2012Assignee: Panasonic CorporationInventors: Zhiqiang Wei, Ryotaro Azuma, Takeshi Takagi, Mitsuteru Iijima, Yoshihiko Kanzawa
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Patent number: 8295123Abstract: In a current rectifying element (10), a barrier height ?A of a center region (14) of a barrier layer (11) in a thickness direction thereof sandwiched between a first electrode layer (12) and a second electrode layer (13) is formed to be larger than a barrier height ?B of a region in the vicinity of an interface (17) between the barrier layer (11) and the first electrode layer (12) and an interface (17) between the barrier layer (11) and the second electrode layer (13). The barrier layer (11) has, for example, a triple-layer structure of barrier layers (11a), (11b) and (11c). The barrier layers (11a), (11b) and (11c) are, for example, formed by SiN layers of SiNx2, SiNx1, and SiNx1 (X1<X2). Therefore, the barrier layer (11) has a barrier height in which the shape changes in a stepwise manner and the height of the center region 14 is large.Type: GrantFiled: July 11, 2008Date of Patent: October 23, 2012Assignee: Panasonic CorporationInventors: Takeshi Takagi, Takumi Mikawa, Koji Arita, Mitsuteru Iijima, Takashi Okada
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Publication number: 20120170353Abstract: A method for programming a nonvolatile memory device according to the present invention includes a step of detecting an excessively low resistance cell from among a plurality of memory cells (11) (S101); a step of changing the resistance value of a load resistor (121) to a second resistance value smaller than a first resistance value (S103); and a step of causing, by applying a voltage pulse to a series circuit including the excessively low resistance cell and the load resistor (121) having the second resistance value, a variable resistance element (105) included in the excessively low resistance cell to shift to a second high resistance state having a resistance value greater than that of the first low resistance state (S104).Type: ApplicationFiled: June 28, 2011Publication date: July 5, 2012Inventors: Mitsuteru Iijima, Takeshi Takagi, Koji Katayama
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Patent number: 8179714Abstract: Provided is a nonvolatile storage device (200) capable of stably operating without increasing a size of a selection transistor included in each of memory cells. The nonvolatile storage device (200) includes: a semiconductor substrate (301) which has a P-type well (301a) of a first conductivity type; a memory cell array (202) which includes memory cells (M11) or the like each of which includes a variable resistance element (R11) and a transistor (N11) that are formed above the semiconductor substrate (301) and connected in series; and a substrate bias circuit (220) which applies, to the P-type well (301a), a bias voltage in a forward direction with respect to a source and a drain of the transistor (N11), when a voltage pulse for writing is applied to the variable resistance element (R11) included in the selected memory cell (M11) or the like.Type: GrantFiled: October 16, 2009Date of Patent: May 15, 2012Assignee: Panasonic CorporationInventors: Takeshi Takagi, Shunsaku Muraoka, Mitsuteru Iijima, Ken Kawai, Kazuhiko Shimakawa
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Publication number: 20120104351Abstract: A stacking structure in which a stacked body (21) including a first conductive layer (13), a semiconductor layer (17), and a second conductive layer (18) and an interlayer insulating film (16) are alternately stacked in parallel to a substrate, a plurality of columnar electrodes (12) arranged so as to penetrated through the stacking structure in a stacking direction, a variable resistance layer (14) which is disposed between the columnar electrode (12) and the first conductive layer (13) and which has a resistance value that reversibly changes according to an application of an electric signal are included. The variable resistance layer (14) is formed by oxidizing part of the first conductive layer (13). The variable resistance layer (14) and an insulating film for electrically separating the semiconductor layer (17) and the second conductive layer (18) from the columnar electrode (12) are simultaneously formed in a single oxidation process.Type: ApplicationFiled: June 29, 2011Publication date: May 3, 2012Inventors: Zhiqiang Wei, Takeshi Takagi, Mitsuteru Iijima
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Publication number: 20110299322Abstract: A method of programming a variable resistance element includes: performing a writing step by applying a writing voltage pulse having a first polarity to a transition metal oxide comprising two metal oxide layers which are stacked, so as to change a resistance state of the transition metal oxide from high to low, each of the two metal oxide layers having a different degree of oxygen deficiency; and performing an erasing step by applying an erasing voltage pulse having a second polarity to the transition metal oxide so as to change the resistance state of the transition metal oxide from low to high, the second polarity being different from the first polarity, wherein |Vw1|>|Vw2| is satisfied, where Vw1 represents a voltage value of the writing voltage pulse for first to N-th writing steps, and Vw2 represents a voltage value of the writing voltage pulse for (N+1)-th and subsequent writing steps, where N is equal to or more than 1, te1>te2 is satisfied, where te1 represents a pulse width of the erasing voltType: ApplicationFiled: February 1, 2011Publication date: December 8, 2011Inventors: Mitsuteru Iijima, Takeshi Takagi
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Publication number: 20110164447Abstract: A current steering element which can prevent occurrence of write disturb even when electric pulses having different polarities are applied and can cause large current to flow through a variable resistance element, and with which data can be written without problem. In a storage element (3) including: a variable resistance element (1) whose electric resistance value changes in response to application of electric pulses having a positive polarity and a negative polarity and which maintains the changed electric resistance value; and the current steering element (2) that steers current flowing through the variable resistance element (1) when the electric pulses are applied, the current steering element (2) includes: a first electrode (32); a second electrode (31); and a current steering layer (33) interposed between the first electrode (32) and the second electrode (31). When the current steering layer (33) includes SiNx (0<x?0.Type: ApplicationFiled: September 17, 2009Publication date: July 7, 2011Inventors: Koji Arita, Takumi Mikawa, Mitsuteru Iijima, Kenji Tominaga
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Publication number: 20110103132Abstract: Provided are a nonvolatile memory element which is capable of effectively preventing an event that when a failure occurs in a certain nonvolatile memory element, data cannot be written to and read from another nonvolatile memory element belonging to the same column or row as that to which the nonvolatile memory element in a failed state belongs, and a semiconductor memory device including the nonvolatile memory element.Type: ApplicationFiled: April 22, 2010Publication date: May 5, 2011Inventors: Zhiqiang Wei, Takeshi Takagi, Mitsuteru Iijima
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Publication number: 20110075469Abstract: Each of memory cells (MC) includes one transistor and one resistance variable element. The transistor includes a first main terminal, a second main terminal and a control terminal. The resistance variable element includes a first electrode, a second electrode and a resistance variable layer provided between the first electrode and the second electrode. A first main terminal of one of two adjacent memory cells is connected to a second main terminal of the other memory cell, to form a series path (SP) sequentially connecting main terminals of the plurality of memory cells in series.Type: ApplicationFiled: March 15, 2010Publication date: March 31, 2011Inventors: Zhiqiang Wei, Ryotaro Azuma, Takeshi Takagi, Mitsuteru Iijima, Yoshihiko Kanzawa