Abstract: In an electronic circuit system unit having a semiconductor integrated circuit unit on a wafer scale, a semiconductor wafer (a semiconductor integrated circuit unit on a wafer scale) and a print wiring substrate are laid to overlap each other and semiconductor pellets are mounted on the print wiring substrate in the overlapping area of the print wiring substrate and the semiconductor wafer. In said electronic circuit system unit, an area being a part of the periphery of the semiconductor wafer is protruded from the periphery of the print wiring substrate being placed to overlap the semiconductor wafer, and the semiconductor wafer and the print wiring substrate are electrically connected to each other in an area being a part of the protruded part through wires.

Abstract: In LSI circuit devices having a plurality of subchips packaged therein and having specific functions, capacitance cutting buffer circuits are employed in conjunction with respective terminals of the subchips, and a driver is disposed at respective points where relatively long wiring lines are respectively sub-divided into a corresponding plurality of lines. As a result, signal transmission delay can be significantly reduced. The terminals of the subchips are also provided with a probing pad to test the operations of the subchips independently of one another. The subchips employ circuit blocks which are to operate simultaneously and in conjunction with the wirings of the subchips, power supply lines are disposed correspondingly to the distributively arranged circuit blocks. Bus lines also controllably transmit addresses as well as data signals in a time sharing manner. Furthermore, each of the subchips has a fault test circuit.

Abstract: A plurality of unit integrated circuits mounted on a large-scale integrated circuit device, for example, a wafer scale memory, are each provided with a bypass circuit which selectively shorts input and output nodes in the corresponding unit integrated circuit. By selectively bringing the bypass circuit into a transfer state, it is possible to effectively couple together all unit integrated circuits which are judged to be normal among a plurality of unit integrated circuits disposed along one row, for example. Improved redundancy arrangements are also provided, including first and second redundant elements for the unit integrated circuits, to effectively utilize the normal elements in the unit integrated circuits. Further, an improved arrangement for hierarchically connecting together the outputs of all the unit circuit blocks is provided which reduces the signal line load for the memory device.