Abstract: A method is provided that includes forming a bit line above the substrate, the bit line disposed in a first direction, after forming the bit line, forming a word line above a substrate, the word line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, resistive memory elements located in the alternating stack in first and second array regions and contact via structures located in a contact region between the first and the second array regions. The contact via structures have different depths and contact different electrically conductive layers. Support pillars are located in the contact region and extending through the alternating stack. At least one conduction channel area is located between the contact via structures in the contact region. The conduction channel area contains no support pillars, and all electrically conductive layers in the conduction channel area are continuous from the first array region to the second array region.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, an array of memory structures, conductive structures located between a substrate and the alternating stack, conductive via structures, including an upper portion that overlies and contacts a top surface of a respective one of the electrically conductive layers, and a lower portion that underlies and is adjoined to the upper portion, contacts a top surface of a respective one of the conductive structures, and is electrically insulated from the rest of the electrically conductive layers. Inner, outer and intermediate dielectric spacers laterally surround a respective one of the conductive via structures.

Abstract: A method is provided that includes forming a dielectric material and a first sacrificial material above a substrate, forming a second sacrificial material above the substrate and disposed adjacent the dielectric material and the first sacrificial material, forming a first hole in the second sacrificial material, the first hole disposed in a first direction, forming a word line layer above the substrate via the first hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a first portion of a nonvolatile memory material on peripheral sides of the word line layer via the first hole, forming a second hole in the second sacrificial material, forming a second portion of the nonvolatile memory material on a sidewall of the second hole, forming a local bit line in the second hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.

Abstract: A method is provided that includes forming a dielectric material and a first sacrificial material above a substrate, forming a second sacrificial material above the substrate and disposed adjacent the dielectric material and the first sacrificial material, forming a first hole in the second sacrificial material, the first hole disposed in a first direction, forming a word line layer above the substrate via the first hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a first portion of a nonvolatile memory material on peripheral sides of the word line layer via the first hole, forming a second hole in the second sacrificial material, forming a second portion of the nonvolatile memory material on a sidewall of the second hole, forming a local bit line in the second hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.

Abstract: The source region and gate electrode of a field effect transistor including a drain region and a gate electrode in addition to the source region are connected by a first ferroelectric capacitor. The drain region and gate electrode are connected by a second ferroelectric capacitor. A ferroelectric memory device suitable for high integration is provided.