Patents by Inventor Mitsutoshi Sawano
Mitsutoshi Sawano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10405434Abstract: A mounting jig for a semiconductor device includes an insulated circuit board positioning jig having a concave part in which an insulated circuit board is placed, a tubular contact element positioning jig disposed on an upper side of the insulated circuit board and having a plurality of positioning holes at predetermined positions to insert a plurality of tubular contact elements respectively, and a tubular contact element press-down jig having a flat plate and a plurality of projections extending from a lower surface of the flat plate. The plurality of projections includes a first length from the flat plate on a side closer to an outer circumference of the insulated circuit board, and a second length from the flat plate inside the outer circumference of the insulated circuit board. The first length is shorter than the second length.Type: GrantFiled: August 8, 2017Date of Patent: September 3, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Rikihiro Maruyama, Kenshi Kai, Nobuyuki Kanzawa, Mitsutoshi Sawano
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Patent number: 9877397Abstract: A mounting jig for a semiconductor device includes an insulated circuit board positioning jig positioning an insulated circuit board by housing the insulated circuit board at a predetermined position, a tubular contact element positioning jig having a plurality of positioning holes at predetermined positions to insert a plurality of tubular contact elements respectively, and a tubular contact element press-down jig for pressing down the plurality of tubular contact elements inserted into the respective positioning holes in the tubular contact element positioning jig.Type: GrantFiled: October 27, 2015Date of Patent: January 23, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Rikihiro Maruyama, Kenshi Kai, Nobuyuki Kanzawa, Mitsutoshi Sawano
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Publication number: 20170339794Abstract: A mounting jig for a semiconductor device includes an insulated circuit board positioning jig having a concave part in which an insulated circuit board is placed, a tubular contact element positioning jig disposed on an upper side of the insulated circuit board and having a plurality of positioning holes at predetermined positions to insert a plurality of tubular contact elements respectively, and a tubular contact element press-down jig having a flat plate and a plurality of projections extending from a lower surface of the flat plate. The plurality of projections includes a first length from the flat plate on a side closer to an outer circumference of the insulated circuit board, and a second length from the flat plate inside the outer circumference of the insulated circuit board. The first length is shorter than the second length.Type: ApplicationFiled: August 8, 2017Publication date: November 23, 2017Inventors: Rikihiro MARUYAMA, Kenshi KAI, Nobuyuki KANZAWA, Mitsutoshi SAWANO
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Publication number: 20160050764Abstract: A mounting jig for a semiconductor device includes an insulated circuit board positioning jig positioning an insulated circuit board by housing the insulated circuit board at a predetermined position, a tubular contact element positioning jig having a plurality of positioning holes at predetermined positions to insert a plurality of tubular contact elements respectively, and a tubular contact element press-down jig for pressing down the plurality of tubular contact elements inserted into the respective positioning holes in the tubular contact element positioning jig.Type: ApplicationFiled: October 27, 2015Publication date: February 18, 2016Inventors: Rikihiro MARUYAMA, Kenshi KAI, Nobuyuki KANZAWA, Mitsutoshi SAWANO
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Patent number: 9204559Abstract: A method of manufacturing a semiconductor device uses a mounting jig having an insulated circuit board positioning jig, a tubular contact element positioning jig having a plurality of positioning holes formed at predetermined positions to insert a tubular contact element, and a tubular contact element press-down jig. By the insulated circuit board positioning jig and tubular contact element positioning jig, an insulated circuit board and the tubular contact elements are positioned, and the tubular contact elements are soldered to the insulated circuit board while being pressed down by the tubular contact element press-down jig.Type: GrantFiled: March 11, 2014Date of Patent: December 1, 2015Assignee: FUJI ELECTRIC CO., LTD.Inventors: Rikihiro Maruyama, Kenshi Kai, Nobuyuki Kanzawa, Mitsutoshi Sawano
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Publication number: 20140317896Abstract: A method of manufacturing a semiconductor device uses a mounting jig having an insulated circuit board positioning jig, a tubular contact element positioning jig having a plurality of positioning holes formed at predetermined positions to insert a tubular contact element, and a tubular contact element press-down jig. By the insulated circuit board positioning jig and tubular contact element positioning jig, an insulated circuit board and the tubular contact elements are positioned, and the tubular contact elements are soldered to the insulated circuit board while being pressed down by the tubular contact element press-down jig.Type: ApplicationFiled: March 11, 2014Publication date: October 30, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventors: Rikihiro MARUYAMA, Kenshi KAI, Nobuyuki KANZAWA, Mitsutoshi SAWANO
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Patent number: 8748225Abstract: A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 ?m or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip.Type: GrantFiled: April 10, 2013Date of Patent: June 10, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Kyohei Fukuda, Eiji Mochizuki, Mitsutoshi Sawano, Takaaki Suzawa
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Patent number: 8598688Abstract: A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 ?m or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip.Type: GrantFiled: June 10, 2011Date of Patent: December 3, 2013Assignee: Fuji Electric Co., Ltd.Inventors: Kyohei Fukuda, Eiji Mochizuki, Mitsutoshi Sawano, Takaaki Suzawa
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Publication number: 20130237016Abstract: A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 ?m or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip.Type: ApplicationFiled: April 10, 2013Publication date: September 12, 2013Applicant: FUJI ELECTRIC CO., LTD.Inventors: Kyohei FUKUDA, Eiji MOCHIZUKI, Mitsutoshi SAWANO, Takaaki SUZAWA
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Publication number: 20120313224Abstract: A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 ?m or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: FUJI ELECTRIC CO., LTD.Inventors: Kyohei FUKUDA, Eiji MOCHIZUKI, Mitsutoshi SAWANO, Takaaki SUZAWA
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Patent number: 6418030Abstract: A multi-chip module includes bare IC chips mounted on respective areas of a printed wiring board. Outer electrode pads on the peripheries of the board are soldered to another printed wiring board such as a motherboard. Lead pads and the outer electrode pads are interconnected through a circuit pattern, through holes, and interstitial via holes. The circuit pattern is disposed on a die bonding surface of the bare IC chips for which insulation is not necessary.Type: GrantFiled: August 11, 2000Date of Patent: July 9, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Masayoshi Yamaguchi, Mitsutoshi Sawano, Kazutoshi Hohki
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Patent number: 6147876Abstract: Bare IC chips (201 through 203) are mounted on respective areas (101 through 103) of a printed wiring board (100). The outer electrode pads (105) on the peripheries of the board (100) are soldered to another printed wiring board (1) such as a mother board. Lead pads (107) and the outer electrode pads (105) are interconnected through a circuit pattern (109), through holes (111) and interstitial via holes (112). The circuit pattern (109) is disposed on a die bonding surface of the bare IC chips (201 and 202) for which insulation is not necessary. A multi-chip module is thus completed.Type: GrantFiled: June 13, 1996Date of Patent: November 14, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Masayoshi Yamaguchi, Mitsutoshi Sawano, Kazutoshi Hohki