Abstract: A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

Abstract: A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

Abstract: A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

Abstract: A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

Abstract: A semiconductor device having at least three independently accessible memories, with at least one of the memories having a different memory capacity than the others. Separate selection signals are provided to the memories so that they can be independently activated. This allows the memories to be separately tested. When testing the semiconductor device, the memories are tested serially, except for the memory with the largest capacity, since this memory also has the longest test time. The memory with the longest test time is tested in parallel with the serially tested memories. This reduces the current that must be supplied by a test device to the semiconductor device during testing.

Abstract: A semiconductor integrated circuit device has a normal mode and a test mode for testing a memory thereof, and comprises input/output buffer parts having input/output terminals, at least one gate array, at least one memory, a first interconnection for coupling the input/output buffer parts, the gate array and the memory and routed depending on a logic operation to be carried out by the semiconductor integrated circuit, and a second interconnection for coupling the input/output buffer parts, the gate array and the memory, where the second interconnection is fixed regardless of the logic operation to be carried out by the semiconductor integrated circuit.

Abstract: A compound transistor type inverter, i.e., comprised of MIS and bipolar transistors, including, at the output stage thereof, an npn transistor operative to charge a load. The npn transistor can be quickly cut OFF by an additional transistor, and simultaneously, the additional transistor is operative to attain a quick discharge from the load. Still another additional transistor is employed, in a case where the inverter includes a pnp transistor, other than the npn transistor, at a ground side, which another additional transistor is operative to bypass the collector and emitter of the pnp transistor.