Patents by Inventor Mitsuyasu Ohta

Mitsuyasu Ohta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7348595
    Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: March 25, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Sadami Takeoka, Mitsuyasu Ohta, Osamu Ichikawa, Masayoshi Yoshimura
  • Patent number: 7302658
    Abstract: In evaluating of the quality of test sequences for delay faults, when all the delay faults are equally regarded, the process of detecting the delay faults deserving to be detected and those not so deserving to be detected cannot be reflected on the quality evaluation for the test sequences. To solve the problem, a “design delay value” on a signal path, on which a corresponding delay fault is defined, is weighted. This invention thus provides “methods of evaluating the quality of test sequences for delay faults” capable of evaluating the quality of the “delay fault test sequences” with more accuracy.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: November 27, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Sadami Takeoka, Mitsuyasu Ohta
  • Publication number: 20070250284
    Abstract: A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.
    Type: Application
    Filed: February 28, 2007
    Publication date: October 25, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Sadami Takeoka, Mitsuyasu Ohta, Osamu Ichikawa, Masayoshi Yoshimura, Takashi Ishimura
  • Publication number: 20070106965
    Abstract: Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting from this grouping. With the outputs from the terminals Q of the flip-flop circuits thus fixed, an operation of a shift mode is carried out. When the operation of the shift mode is completed, a hold releasing operation and a capture operation are carried out with respect to each of the groups of the flip-flop circuits. For example, the hold releasing operation is carried out when one clock is at a high level with the capture operation carried out when the clock is at a low level, or the hold releasing operation is successively carried out with respect to each of the groups and then the capture operation for capturing a data signal is carried out with respect to each of the groups.
    Type: Application
    Filed: December 28, 2006
    Publication date: May 10, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuyasu Ohta, Sadami Takeoka
  • Patent number: 7203913
    Abstract: Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting from this grouping. With the outputs from the terminals Q of the flip-flop circuits thus fixed, an operation of a shift mode is carried out. When the operation of the shift mode is completed, a hold releasing operation and a capture operation are carried out with respect to each of the groups of the flip-flop circuits. For example, the hold releasing operation is carried out when one clock is at a high level with the capture operation carried out when the clock is at a low level, or the hold releasing operation is successively carried out with respect to each of the groups and then the capture operation for capturing a data signal is carried out with respect to each of the groups.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: April 10, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuyasu Ohta, Sadami Takeoka
  • Patent number: 7197725
    Abstract: A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: March 27, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Sadami Takeoka, Mitsuyasu Ohta, Osamu Ichikawa, Masayoshi Yoshimura, Takashi Ishimura
  • Patent number: 7171600
    Abstract: An apparatus for testing a semiconductor device by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, including a silicon wiring substrate on which the chip IPs are mounted. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip-flops to wiring, which are arranged to test connections in the wiring. An IP on Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: January 30, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Sadami Takeoka, Mitsuyasu Ohta, Osamu Ichikawa, Masayoshi Yoshimura
  • Publication number: 20070011543
    Abstract: A high-quality test pattern for testing a delay fault is generated at a high speed. In order that a second test pattern provided at a test cycle that follows a test cycle should be generated, a fault value set up in a circuit is propagated to an observation point. At a branch point in the circuit, a signal line for propagating the fault value is selected from the branches. Then, activation and justification are performed so that a value of the signal line in the circuit is acquired. When the activation and the justification have been successful, the second test pattern is updated on the basis of the acquired value of the signal line. In the selection of the signal line, one of branches is selected on the basis of the length of the longest path from each branch to the observation point.
    Type: Application
    Filed: June 6, 2006
    Publication date: January 11, 2007
    Inventors: Shinichi Yoshimura, Tomokazu Miura, Mitsuyasu Ohta, Osamu Ichikawa
  • Patent number: 7032196
    Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: April 18, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Sadami Takeoka, Mitsuyasu Ohta, Osamu Ichikawa, Masayoshi Yoshimura
  • Publication number: 20050010839
    Abstract: In evaluating of the quality of test sequences for delay faults, when all the delay faults are equally regarded, the process of detecting the delay faults deserving to be detected and those not so deserving to be detected cannot be reflected on the quality evaluation for the test sequences. To solve the problem, a “design delay value” on a signal path, on which a corresponding delay fault is defined, is weighted. This invention thus provides “methods of evaluating the quality of test sequences for delay faults” capable of evaluating the quality of the “delay fault test sequences” with more accuracy.
    Type: Application
    Filed: January 28, 2004
    Publication date: January 13, 2005
    Inventors: Sadami Takeoka, Mitsuyasu Ohta
  • Publication number: 20040195672
    Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
    Type: Application
    Filed: April 21, 2004
    Publication date: October 7, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Sadami Takeoka, Mitsuyasu Ohta, Osamu Ichikawa, Masayoshi Yoshimura
  • Publication number: 20040199840
    Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
    Type: Application
    Filed: April 21, 2004
    Publication date: October 7, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Sadami Takeoka, Mitsuyasu Ohta, Osamu Ichikawa, Masayoshi Yoshimura
  • Publication number: 20040197941
    Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
    Type: Application
    Filed: April 21, 2004
    Publication date: October 7, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Sadami Takeoka, Mitsuyasu Ohta, Osamu Ichikawa, Masayoshi Yoshimura
  • Publication number: 20040139376
    Abstract: A semiconductor integrated circuit (1) includes first, second and second functional blocks (10, 20 and 30). The first, second and second functional blocks (10, 20 and 30) are coupled together via an inter-block signal line (2). The first functional block (10) includes: a logic circuit (11); a test data output circuit (12), which operates during testing and outputs a predetermined test data pattern; a testing standby circuit (14), which is connected between a selector (13) and an external bidirectional pin and makes the functional block enter a standby state during testing; a tristate buffer (15) that is made to have a high impedance by the testing standby circuit (14); and a decision result output circuit (16), which receives the test data pattern from the second functional block, compares the received test data pattern to an expected value stored therein, and outputs a decision result to a decision result signal line (5).
    Type: Application
    Filed: January 6, 2004
    Publication date: July 15, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Mitsuyasu Ohta, Sadami Takeoka, Toshihiro Hiraoka
  • Patent number: 6734549
    Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: May 11, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Sadami Takeoka, Mitsuyasu Ohta, Osamu Ichikawa, Masayoshi Yoshimura
  • Patent number: 6708301
    Abstract: A semiconductor integrated circuit (1) includes first, second and second functional blocks (10, 20 and 30). The first, second and second functional blocks (10, 20 and 30) are coupled together via an inter-block signal line (2). The first functional block (10) includes: a logic circuit (11); a test data output circuit (12), which operates during testing and outputs a predetermined test data pattern; a testing standby circuit (14), which is connected between a selector (13) and an external bidirectional pin and makes the functional block enter a standby state during testing; a tristate buffer (15) that is made to have a high impedance by the testing standby circuit (14); and a decision result output circuit (16), which receives the test data pattern from the second functional block, compares the received test data pattern to an expected value stored therein, and outputs a decision result to a decision result signal line (5).
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: March 16, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuyasu Ohta, Sadami Takeoka, Toshihiro Hiraoka
  • Patent number: 6651206
    Abstract: Flip-flops (FFs) to replace with scan FFs are selected for an integrated circuit designed at the gate level in order that the integrated circuit has an n-fold line-up structure. All FFs in an integrated circuit are temporarily selected as FFs to replace with scan FFs Each FF to replace with a scan FF is temporarily selected as a FF to replace with a non-scan flip-flop, and the structure of the integrated circuit is checked if it has an n-folded line-up structure and if so, then the FF is selected as a FF to replace with a non-scan flip-flop. For an integrated circuit designed at the gate level, flip-flops to replace with scan flip-flops are selected in order that the integrated circuit has an n-fold line-up structure, without recognizing load/hold FFs as self-loop structure FF. Thereafter, FFs to replace with scan FFs are selected in such a way as to facilitate testing on load/hold FFs.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: November 18, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshinori Hosokawa, Mitsuyasu Ohta
  • Patent number: 6625784
    Abstract: Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting from this grouping. With the outputs from the terminals Q of the flip-flop circuits thus fixed, an operation of a shift mode is carried out. When the operation of the shift mode is completed, a hold releasing operation and a capture operation are carried out with respect to each of the groups of the flip-flop circuits. For example, the hold releasing operation is carried out when one clock is at a high level with the capture operation carried out when the clock is at a low level, or the hold releasing operation is successively carried out with respect to each of the groups and then the capture operation for capturing a data signal is carried out with respect to each of the groups.
    Type: Grant
    Filed: August 15, 2000
    Date of Patent: September 23, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuyasu Ohta, Sadami Takeoka
  • Patent number: 6615389
    Abstract: In response to a design request, fault detection strategy optimizing means selects RT-VCs and a fault detection method from a VCDB. The design request includes: requirements for a system LSI (e.g., area, number of pins, test time and information about the weights of prioritized constraints); and VC information. The fault detection strategy optimizing means performs computations for optimization in view of various parameters, thereby specifying a best fault detection strategy and a method of constructing a single-chip fault detection controller. On the VCDB, multiple VCs associated with the same function and mutually different test techniques are stored. By weighting the parameters affecting a test cost in accordance with a user defined priority order, a test technique of the type minimizing the total test cost can be selected from the VCDB.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: September 2, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuyasu Ohta, Sadami Takeoka, Osamu Ichikawa
  • Publication number: 20030046643
    Abstract: Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting from this grouping. With the outputs from the terminals Q of the flip-flop circuits thus fixed, an operation of a shift mode is carried out. When the operation of the shift mode is completed, a hold releasing operation and a capture operation are carried out with respect to each of the groups of the flip-flop circuits. For example, the hold releasing operation is carried out when one clock is at a high level with the capture operation carried out when the clock is at a low level, or the hold releasing operation is successively carried out with respect to each of the groups and then the capture operation for capturing a data signal is carried out with respect to each of the groups.
    Type: Application
    Filed: October 28, 2002
    Publication date: March 6, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Mitsuyasu Ohta, Sadami Takeoka