Abstract: A copy-back type cache memory device using a delayed wait method capable of completing a data-write process in one process cycle. The device includes single word memory means for storing the single word of the selected data in a data memory means when an access for a data-write is made, the single word being located at the address in the data memory means corresponding to the processor address; and copy-back memory means for restoring the superseded data along with other data together with which the superseded data forms a block, so that the block can be reorganized in its original state before the data-write process takes place.

Abstract: Each register of an internal register unit of a microprocessor has a pair of register cells consisting of first and second cells having the same register address. When one of these cells is selected, the other cell non-selected serves as a "back-up cell" for the selected cell. Each register of the register unit has a flag bit for storing a selector flag representing which cell of the pair of cells of the register is currently selected, and a flag bit for storing a change flag representing whether register information of the register is rewritten after a selected cell is changed between the first and second cells of the register. When the register information is stored in one of the pair of cells currently being selected of a certain register and is to be rewritten with another new information, the other cell of the register is selected to store the new information therein.

Abstract: A cache memory device comprises a data cache memory, an instruction cache memory, an instruction code area change detector, and an instruction code change processor. The instruction code area change detector decides whether writing access to the data cache memory by the processor is to a data area or to an instruction area of a main memory. The instruction code change processor passes the data cache memory to perform direct writing into the main memory when the writing access is to the instruction area, and, when data for a processor address is cached in a tag section of the instruction cache memory, invalidates the effective flag of the tag section.

Abstract: A register device includes a register set group, a switching control unit, a write control unit, a write flag memory unit, and a read control unit. The register set group consists of a plurality of register sets each constituted by a plurality of registers. The switching control unit selects a register set to be used in processing from the register set group in response to a saving/recovery instruction. The write control unit writes data in registers of the register set selected by the switching control unit in response to a write instruction. A write flag representing whether data is written in each of the registers is held by the write flag memory unit. The read control unit determines, in response to a read instruction, a register in which data is written most recently of a plurality of registers corresponding to each other between the register sets with reference to the write flags, thereby reading out data from the register.

Abstract: The character reading system is provided with a pretreating system for a pattern recognition and a picture translation wherein a pattern signal obtained by scanning a character pattern on a recording medium is processed at such high threshold level that does not contain a noise component to form a primary kernel pattern, and the pattern signal is processed at such low threshold level that contains said character pattern to obtain a reference pattern. The kernel pattern and the reference pattern are masked on a memory device to have predetermined size and subjected to connecting operation when they are read out by forward scanning to form a connected secondary kernel pattern. The secondary kernel pattern and the reference pattern are masked to have predetermined size and then reversely scanned to subject both patterns to the second connecting operation thereby producing a last kernel pattern.