Patents by Inventor Mitsuyoshi Takeda

Mitsuyoshi Takeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6229196
    Abstract: The semiconductor device includes a semiconductor base body (11) formed of a damaged layer (102) serving as a gettering layer, a P+ collector layer (103), an N+ buffer layer (104), and an N− layer (105) laid one on top of another, a gate electrode (27) selectively formed on the upper main surface of the semiconductor base body (11) specifically on the external main surface of the N− layer (105), with a gate insulating film (26) interposed therebetween, an emitter electrode (28) selectively formed on the upper main surface of the semiconductor base body (11), and a collector electrode (106) formed on the lower main surface of the semiconductor base body (11), specifically on the external main surface of the damaged layer (102).
    Type: Grant
    Filed: January 6, 1998
    Date of Patent: May 8, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuyasu Shishido, Mitsuyoshi Takeda, Yoshifumi Tomomatsu
  • Patent number: 5945691
    Abstract: In order to inhibit destruction during a turn-off state, a cathode electrode (6) is not connected to the overall major surface of a semiconductor substrate (10), but selectively connected to a region which is substantially opposed to an anode electrode (5). When a forward voltage is applied, therefore, an electric field which is generated in the semiconductor substrate (10) is distributed substantially only in a region immediately under a P-type diffusion layer (2), to hardly spread into a peripheral region positioned outside the region. Consequently, carriers which are injected from the P-type diffusion layer (2) and an N.sup.+ layer (4) into an N.sup.- layer (1) hardly spread to the peripheral region, but are stored substantially only in the region immediately under the P-type diffusion layer (2). Thus, concentration of a reverse current is relieved during a turn-off state in a peripheral edge portion of the P-type diffusion layer (2).
    Type: Grant
    Filed: December 5, 1995
    Date of Patent: August 31, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshifumi Tomomatsu, Mitsuyoshi Takeda, Noriyuki Soejima